[ARM] Fix PR 45726: invalid instruction on arm9tdmi.

Submitted by Richard Earnshaw on Sept. 20, 2010, 4:24 p.m.


Message ID 1284999894.13878.43.camel@e102346-lin.cambridge.arm.com
State New
Headers show

Commit Message

Richard Earnshaw Sept. 20, 2010, 4:24 p.m.
On Mon, 2010-09-20 at 16:35 +0100, Richard Earnshaw wrote:
> PR 45726 is a wrong code bug on ARM where we accidentally emit an
> instruction to perform a bitfield-insert-immediate on machines with no
> support for MOVT.  The patch is pretty trivial, we just disable the
> pattern on machines without MOVT.
> Committed to 4.5 branch and trunk.
> R.
> 2010-09-20  Rafael Carre   <rafael.carre@gmail.com>
> 	PR target/45726
> 	* arm.md (arm_movtas_ze): Only enable on machine with MOVT.

I missed a second part to this patch.  There's another instruction
pattern that is incorrectly enabled for all 32-bit compiles: arm_movt.

I think in this case the compiler will never end up generating this
pattern spontaneously, so for the moment I've only committed this to

2010-09-20  Rafael Carre   <rafael.carre@gmail.com>

	PR target/45726
	* arm.md (arm_movt): Only enable on machines with MOVT.

Patch hide | download patch | download mbox

Index: gcc/config/arm/arm.md
--- gcc/config/arm/arm.md	(revision 164440)
+++ gcc/config/arm/arm.md	(working copy)
@@ -5119,7 +5119,7 @@  (define_insn "*arm_movt"
   [(set (match_operand:SI 0 "nonimmediate_operand" "=r")
 	(lo_sum:SI (match_operand:SI 1 "nonimmediate_operand" "0")
 		   (match_operand:SI 2 "general_operand"      "i")))]
+  "arm_arch_thumb2"
   "movt%?\t%0, #:upper16:%c2"
   [(set_attr "predicable" "yes")
    (set_attr "length" "4")]