diff mbox

[U-Boot] armv8: fsl-layerscape: mmu: Fix enabling MMU

Message ID 1469209943-31930-1-git-send-email-york.sun@nxp.com
State Accepted
Commit ed7a3943d580f4cf72e5ef8a20c43fa93e889d14
Delegated to: York Sun
Headers show

Commit Message

York Sun July 22, 2016, 5:52 p.m. UTC
MMU bit in SCTLR needs to be set explicitly after tables are
created. It isn't an issue for EL3 becuase this bit is already
set by early MMU setup. But for other exception levels this
bit was not set.

Signed-off-by: York Sun <york.sun@nxp.com>
---
Setting CR_M bit wasn't needed for this function when U-Boot runs at EL3.
Recent additional of PPA, and pending change of distro boot requires MMU
to be setup for EL2. This bit needs to be set in _this_ function.

Verified on LS1043ARDB with PPA.
Verified on LS2080ARDB with distro boot (Alex Graf's patch set)

 arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

Comments

York Sun July 26, 2016, 8:25 p.m. UTC | #1
On 07/22/2016 10:52 AM, York Sun wrote:
> MMU bit in SCTLR needs to be set explicitly after tables are
> created. It isn't an issue for EL3 becuase this bit is already
> set by early MMU setup. But for other exception levels this
> bit was not set.
>
> Signed-off-by: York Sun <york.sun@nxp.com>
> ---
> Setting CR_M bit wasn't needed for this function when U-Boot runs at EL3.
> Recent additional of PPA, and pending change of distro boot requires MMU
> to be setup for EL2. This bit needs to be set in _this_ function.
>
> Verified on LS1043ARDB with PPA.
> Verified on LS2080ARDB with distro boot (Alex Graf's patch set)
>
>  arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 5 ++++-
>  1 file changed, 4 insertions(+), 1 deletion(-)

Applied to fsl-qoriq master. Awaiting upstream.

York
diff mbox

Patch

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index 752ccb0..f000a6a 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -146,11 +146,14 @@  static inline void final_mmu_setup(void)
 	set_ttbr_tcr_mair(el, gd->arch.tlb_addr, get_tcr(el, NULL, NULL),
 			  MEMORY_ATTRIBUTES);
 	/*
-	 * MMU is already enabled, just need to invalidate TLB to load the
+	 * EL3 MMU is already enabled, just need to invalidate TLB to load the
 	 * new table. The new table is compatible with the current table, if
 	 * MMU somehow walks through the new table before invalidation TLB,
 	 * it still works. So we don't need to turn off MMU here.
+	 * When EL2 MMU table is created by calling this function, MMU needs
+	 * to be enabled.
 	 */
+	set_sctlr(get_sctlr() | CR_M);
 }
 
 u64 get_page_table_size(void)