diff mbox

[U-Boot] ARM: uniphier: add clock/reset settings for xHCI of ProXstream2

Message ID 1469186411-5623-1-git-send-email-yamada.masahiro@socionext.com
State Accepted
Delegated to: Masahiro Yamada
Headers show

Commit Message

Masahiro Yamada July 22, 2016, 11:20 a.m. UTC 
Deassert resets and enable clock signals of xHCI blocks if the
corresponding CONFIG is enabled.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
---

 arch/arm/mach-uniphier/clk/clk-pxs2.c | 7 ++++++-
 arch/arm/mach-uniphier/sc-regs.h      | 4 ++++
 2 files changed, 10 insertions(+), 1 deletion(-)

Comments

Masahiro Yamada July 23, 2016, 3:50 p.m. UTC | #1 
2016-07-22 20:20 GMT+09:00 Masahiro Yamada <yamada.masahiro@socionext.com>:
> Deassert resets and enable clock signals of xHCI blocks if the
> corresponding CONFIG is enabled.
>
> Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
>
Applied to u-boot-uniphier/master.
diff mbox

Patch

diff --git a/arch/arm/mach-uniphier/clk/clk-pxs2.c b/arch/arm/mach-uniphier/clk/clk-pxs2.c
index 76bf856..0d92405 100644
--- a/arch/arm/mach-uniphier/clk/clk-pxs2.c
+++ b/arch/arm/mach-uniphier/clk/clk-pxs2.c
@@ -4,6 +4,7 @@ 
  * SPDX-License-Identifier:	GPL-2.0+
  */
 
+#include <linux/bitops.h>
 #include <linux/io.h>
 
 #include "../init.h"
@@ -32,12 +33,16 @@  void uniphier_pxs2_clk_init(void)
 	tmp |= SC_RSTCTRL2_NRST_USB3B1;
 	writel(tmp, SC_RSTCTRL2);
 	readl(SC_RSTCTRL2); /* dummy read */
+
+	tmp = readl(SC_RSTCTRL6);
+	tmp |= 0x37;
+	writel(tmp, SC_RSTCTRL6);
 #endif
 
 	/* provide clocks */
 	tmp = readl(SC_CLKCTRL);
 #ifdef CONFIG_USB_XHCI_UNIPHIER
-	tmp |= SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
+	tmp |= BIT(20) | BIT(19) | SC_CLKCTRL_CEN_USB31 | SC_CLKCTRL_CEN_USB30 |
 		SC_CLKCTRL_CEN_GIO;
 #endif
 #ifdef CONFIG_UNIPHIER_ETH
diff --git a/arch/arm/mach-uniphier/sc-regs.h b/arch/arm/mach-uniphier/sc-regs.h
index a095589..98f1dea 100644
--- a/arch/arm/mach-uniphier/sc-regs.h
+++ b/arch/arm/mach-uniphier/sc-regs.h
@@ -68,6 +68,10 @@ 
 #define SC_RSTCTRL4_NRST_UMC31		(0x1 <<  5)	/* UMC ch1 */
 #define SC_RSTCTRL4_NRST_UMC30		(0x1 <<  4)	/* UMC ch0 */
 
+#define SC_RSTCTRL5			(SC_BASE_ADDR | 0x2010)
+
+#define SC_RSTCTRL6			(SC_BASE_ADDR | 0x2014)
+
 #define SC_CLKCTRL			(SC_BASE_ADDR | 0x2104)
 #define SC_CLKCTRL_CEN_USB31		(0x1 << 17)	/* USB3 #1 */
 #define SC_CLKCTRL_CEN_USB30		(0x1 << 16)	/* USB3 #0 */