===================================================================
@@ -4212,6 +4212,10 @@ rs6000_option_override_internal (bool global_init_
{
if (rs6000_isa_flags_explicit & OPTION_MASK_P8_FUSION)
{
+ /* We prefer to not mention undocumented options in
+ error messages. However, if users have managed to select
+ power9-fusion without selecting power8-fusion, they
+ already know about undocumented flags. */
error ("-mpower9-fusion requires -mpower8-fusion");
rs6000_isa_flags &= ~OPTION_MASK_P9_FUSION;
}
@@ -4259,6 +4263,10 @@ rs6000_option_override_internal (bool global_init_
/* ISA 3.0 vector instructions include ISA 2.07. */
if (TARGET_P9_VECTOR && !TARGET_P8_VECTOR)
{
+ /* We prefer to not mention undocumented options in
+ error messages. However, if users have managed to select
+ power9-vector without selecting power8-vector, they
+ already know about undocumented flags. */
if (rs6000_isa_flags_explicit & OPTION_MASK_P8_VECTOR)
error ("-mpower9-vector requires -mpower8-vector");
rs6000_isa_flags &= ~OPTION_MASK_P9_VECTOR;
@@ -4286,6 +4294,10 @@ rs6000_option_override_internal (bool global_init_
/* ISA 3.0 D-form instructions require p9-vector and upper-regs. */
if ((TARGET_P9_DFORM_SCALAR || TARGET_P9_DFORM_VECTOR) && !TARGET_P9_VECTOR)
{
+ /* We prefer to not mention undocumented options in
+ error messages. However, if users have managed to select
+ power9-dform without selecting power9-vector, they
+ already know about undocumented flags. */
if (rs6000_isa_flags_explicit & OPTION_MASK_P9_VECTOR)
error ("-mpower9-dform requires -mpower9-vector");
rs6000_isa_flags &= ~(OPTION_MASK_P9_DFORM_SCALAR
@@ -4294,6 +4306,10 @@ rs6000_option_override_internal (bool global_init_
if (TARGET_P9_DFORM_SCALAR && !TARGET_UPPER_REGS_DF)
{
+ /* We prefer to not mention undocumented options in
+ error messages. However, if users have managed to select
+ power9-dform without selecting upper-regs-df, they
+ already know about undocumented flags. */
if (rs6000_isa_flags_explicit & OPTION_MASK_UPPER_REGS_DF)
error ("-mpower9-dform requires -mupper-regs-df");
rs6000_isa_flags &= ~OPTION_MASK_P9_DFORM_SCALAR;
@@ -15507,13 +15523,13 @@ rs6000_invalid_builtin (enum rs6000_builtins fncod
else if ((fnmask & RS6000_BTM_P8_VECTOR) != 0)
error ("Builtin function %s requires the -mpower8-vector option", name);
else if ((fnmask & RS6000_BTM_P9_VECTOR) != 0)
- error ("Builtin function %s requires the -mpower9-vector option", name);
+ error ("Builtin function %s requires the -mcpu=power9 option", name);
else if ((fnmask & (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
== (RS6000_BTM_P9_MISC | RS6000_BTM_64BIT))
- error ("Builtin function %s requires the -mpower9-misc and"
+ error ("Builtin function %s requires the -mcpu=power9 and"
" -m64 options", name);
else if ((fnmask & RS6000_BTM_P9_MISC) == RS6000_BTM_P9_MISC)
- error ("Builtin function %s requires the -mpower9-misc option", name);
+ error ("Builtin function %s requires the -mcpu=power9 option", name);
else if ((fnmask & (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
== (RS6000_BTM_HARD_FLOAT | RS6000_BTM_LDBL128))
error ("Builtin function %s requires the -mhard-float and"
===================================================================
@@ -638,6 +638,7 @@ extern int rs6000_vector_align[];
#define MASK_DIRECT_MOVE OPTION_MASK_DIRECT_MOVE
#define MASK_DLMZB OPTION_MASK_DLMZB
#define MASK_EABI OPTION_MASK_EABI
+#define MASK_FLOAT128 OPTION_MASK_FLOAT128
#define MASK_FPRND OPTION_MASK_FPRND
#define MASK_P8_FUSION OPTION_MASK_P8_FUSION
#define MASK_HARD_FLOAT OPTION_MASK_HARD_FLOAT
@@ -2716,7 +2717,7 @@ extern int frame_pointer_needed;
#define RS6000_BTM_HARD_FLOAT MASK_SOFT_FLOAT /* Hardware floating point. */
#define RS6000_BTM_LDBL128 MASK_MULTIPLE /* 128-bit long double. */
#define RS6000_BTM_64BIT MASK_64BIT /* 64-bit addressing. */
-#define RS6000_BTM_FLOAT128 MASK_P9_VECTOR /* IEEE 128-bit float. */
+#define RS6000_BTM_FLOAT128 MASK_FLOAT128 /* IEEE 128-bit float. */
#define RS6000_BTM_COMMON (RS6000_BTM_ALTIVEC \
| RS6000_BTM_VSX \
===================================================================
@@ -606,7 +606,7 @@ Target Undocumented Var(rs6000_optimize_swaps) Ini
Analyze and remove doubleword swaps from VSX computations.
mpower9-fusion
-Target Report Mask(P9_FUSION) Var(rs6000_isa_flags)
+Target Undocumented Report Mask(P9_FUSION) Var(rs6000_isa_flags)
Fuse certain operations together for better performance on power9.
mpower9-misc
@@ -614,7 +614,7 @@ Target Undocumented Report Mask(P9_MISC) Var(rs600
Use/do not use certain scalar instructions added in ISA 3.0.
mpower9-vector
-Target Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
+Target Undocumented Report Mask(P9_VECTOR) Var(rs6000_isa_flags)
Use/do not use vector instructions added in ISA 3.0.
mpower9-dform-scalar
@@ -626,7 +626,7 @@ Target Undocumented Mask(P9_DFORM_VECTOR) Var(rs60
Use/do not use vector register+offset memory instructions added in ISA 3.0.
mpower9-dform
-Target Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
+Target Undocumented Report Var(TARGET_P9_DFORM_BOTH) Init(-1) Save
Use/do not use register+offset memory instructions added in ISA 3.0.
mpower9-minmax
@@ -638,7 +638,7 @@ Target Undocumented Mask(TOC_FUSION) Var(rs6000_is
Fuse medium/large code model toc references with the memory instruction.
mmodulo
-Target Report Mask(MODULO) Var(rs6000_isa_flags)
+Target Undocumented Report Mask(MODULO) Var(rs6000_isa_flags)
Generate the integer modulo instructions.
mfloat128
===================================================================
@@ -17494,8 +17494,8 @@ int __builtin_bcdsub_gt (vector __int128_t, vector
int __builtin_bcdsub_ov (vector __int128_t, vector__int128_t);
@end smallexample
-If the ISA 3.0 additions to the vector/scalar (power9-vector)
-instruction set are available:
+If the ISA 3.0 instruction set additions (@option{-mcpu=power9})
+are available:
@smallexample
vector long long vec_vctz (vector long long);
@@ -17531,10 +17531,9 @@ vector long long vec_vprtybd (vector long long);
vector unsigned long long vec_vprtybd (vector unsigned long long);
@end smallexample
+On 64-bit targets, if the ISA 3.0 additions (@option{-mcpu=power9})
+are available:
-If the ISA 3.0 additions to the vector/scalar (power9-vector)
-instruction set are available for 64-bit targets:
-
@smallexample
vector long vec_vprtyb (vector long);
vector unsigned long vec_vprtyb (vector unsigned long);
@@ -17549,8 +17548,7 @@ vector __uint128_t vec_vprtybd (vector __uint128_t
@end smallexample
The following built-in vector functions are available for the PowerPC family
-of processors, starting with ISA 3.0 or later (@option{-mcpu=power9})
-or with @option{-mpower9-vector}:
+of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}):
@smallexample
__vector unsigned char
vec_slv (__vector unsigned char src, __vector unsigned char shift_distance);
@@ -17583,8 +17581,7 @@ result returned from the @code{vec_srv} function i
with this resulting value coerced to the @code{unsigned char} type.
The following built-in functions are available for the PowerPC family
-of processors, starting with ISA 3.0 or later (@option{-mcpu=power9})
-or with @option{-mpower9-vector}:
+of processors, starting with ISA 3.0 or later (@option{-mcpu=power9}):
@smallexample
__vector unsigned char
vec_absd (__vector unsigned char arg1, __vector unsigned char arg2);
@@ -17667,9 +17664,9 @@ The second argument to the @var{__builtin_crypto_v
integer that is 0 or 1. The third argument to these builtin functions
must be a constant integer in the range of 0 to 15.
-If the ISA 3.0 additions to the vector/scalar (power9-vector)
-instruction set are available, the following additional functions are
-available for both 32-bit and 64-bit targets.
+If the ISA 3.0 instruction set additions
+are enabled (@option{-mcpu=power9}), the following additional
+functions are available for both 32-bit and 64-bit targets.
vector short vec_xl (int, vector short *);
vector short vec_xl (int, short *);
===================================================================
@@ -1011,10 +1011,9 @@ See RS/6000 and PowerPC Options.
-mcompat-align-parm -mno-compat-align-parm @gol
-mupper-regs-df -mno-upper-regs-df -mupper-regs-sf -mno-upper-regs-sf @gol
-mupper-regs-di -mno-upper-regs-di @gol
--mupper-regs -mno-upper-regs -mmodulo -mno-modulo @gol
+-mupper-regs -mno-upper-regs @gol
-mfloat128 -mno-float128 -mfloat128-hardware -mno-float128-hardware @gol
--mpower9-fusion -mno-mpower9-fusion -mpower9-vector -mno-power9-vector @gol
--mpower9-dform -mno-power9-dform -mlra -mno-lra}
+-mlra -mno-lra}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu@gol
@@ -20110,8 +20109,7 @@ following options:
-mpowerpc-gpopt -mpowerpc-gfxopt -msingle-float -mdouble-float @gol
-msimple-fpu -mstring -mmulhw -mdlmzb -mmfpgpr -mvsx @gol
-mcrypto -mdirect-move -mhtm -mpower8-fusion -mpower8-vector @gol
--mquad-memory -mquad-memory-atomic -mmodulo -mfloat128 -mfloat128-hardware @gol
--mpower9-fusion -mpower9-vector -mpower9-dform}
+-mquad-memory -mquad-memory-atomic -mfloat128 -mfloat128-hardware}
The particular options set for any particular CPU varies between
compiler versions, depending on what setting seems to produce optimal
@@ -20355,7 +20353,7 @@ instructions that target all 64 registers in the v
floating point register set that were added in version 2.07 of the
PowerPC ISA. @option{-mupper-regs-sf} is turned on by default if you
use either of the @option{-mcpu=power8}, @option{-mpower8-vector}, or
-@option{-mpower9} options.
+@option{-mcpu=power9} options.
@item -mupper-regs
@itemx -mno-upper-regs
@@ -20400,40 +20398,6 @@ If you select ISA 3.0 instructions with @option{-m
not use either @option{-mfloat128} or @option{-mfloat128-hardware},
the IEEE 128-bit floating point support will not be enabled.
-@item -mmodulo
-@itemx -mno-modulo
-@opindex mmodulo
-@opindex mno-module
-Generate code that uses (does not use) the ISA 3.0 integer modulo
-instructions. The @option{-mmodulo} option is enabled by default
-with the @option{-mcpu=power9} option.
-
-@item -mpower9-fusion
-@itemx -mno-power9-fusion
-@opindex mpower9-fusion
-@opindex mno-power9-fusion
-Generate code that keeps (does not keeps) some operations adjacent so
-that the instructions can be fused together on power9 and later
-processors.
-
-@item -mpower9-vector
-@itemx -mno-power9-vector
-@opindex mpower9-vector
-@opindex mno-power9-vector
-Generate code that uses (does not use) the vector and scalar
-instructions that were added in version 3.0 of the PowerPC ISA. Also
-enable the use of built-in functions that allow more direct access to
-the vector instructions.
-
-@item -mpower9-dform
-@itemx -mno-power9-dform
-@opindex mpower9-dform
-@opindex mno-power9-dform
-Enable (disable) scalar d-form (register + offset) memory instructions
-to load/store traditional Altivec registers. If the @var{LRA} register
-allocator is enabled, also enable (disable) vector d-form memory
-instructions.
-
@item -mfloat-gprs=@var{yes/single/double/no}
@itemx -mfloat-gprs
@opindex mfloat-gprs
===================================================================
@@ -3038,13 +3038,13 @@ asm ("xsaddqp %x0,%x1,%x2" : "=v" (v1) : "v" (v2),
is incorrect.
@item wb
-Altivec register if @option{-mpower9-dform} is used or NO_REGS.
+Altivec register if @option{-mcpu=power9} is used or NO_REGS.
@item wd
VSX vector register to hold vector double data or NO_REGS.
@item we
-VSX register if the @option{-mpower9-vector} and @option{-m64} options
+VSX register if the @option{-mcpu=power9} and @option{-m64} options
were used or NO_REGS.
@item wf