| Message ID | 1468923862-29784-1-git-send-email-prabhakar.kushwaha@nxp.com |
|---|---|
| State | Accepted |
| Commit | 9c3fca2a79be3d9d67d7766bbd85efc941bcb237 |
| Delegated to: | York Sun |
| Headers | show
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Ip=[192.88.168.50]; Helo=[tx30smr01.am.freescale.net] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN3PR03MB2179 Subject: [U-Boot] [PATCH 1/2] armv8: ls1012a: Enable DDR row-bank-column decoding X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion <u-boot.lists.denx.de> List-Unsubscribe: <http://lists.denx.de/mailman/options/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=unsubscribe> List-Archive: <http://lists.denx.de/pipermail/u-boot/> List-Post: <mailto:u-boot@lists.denx.de> List-Help: <mailto:u-boot-request@lists.denx.de?subject=help> List-Subscribe: <http://lists.denx.de/mailman/listinfo/u-boot>, <mailto:u-boot-request@lists.denx.de?subject=subscribe> Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" <u-boot-bounces@lists.denx.de> |
On 07/19/2016 03:24 AM, Prabhakar Kushwaha wrote: > Enable DDR row-bank-column decoding to decode DDR address as > row-bank-column instead of bank-row-column for improving > performance of serial data transfers. > > Signed-off-by: Calvin Johnson <calvin.johnson@nxp.com> > Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> > --- > include/fsl_mmdc.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Applied to fsl-qoriq master, awaiting upstream. Thanks. York
diff --git a/include/fsl_mmdc.h b/include/fsl_mmdc.h index 281a819..833696b 100644 --- a/include/fsl_mmdc.h +++ b/include/fsl_mmdc.h @@ -12,7 +12,7 @@ #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_1 0xff328f64 #define CONFIG_SYS_MMDC_CORE_TIMING_CFG_2 0x01ff00db -#define CONFIG_SYS_MMDC_CORE_MISC 0x00000680 +#define CONFIG_SYS_MMDC_CORE_MISC 0x00001680 #define CONFIG_SYS_MMDC_PHY_MEASURE_UNIT 0x00000800 #define CONFIG_SYS_MMDC_CORE_RDWR_CMD_DELAY 0x00002000 #define CONFIG_SYS_MMDC_PHY_ODT_CTRL 0x0000022a