diff mbox

[i386] : Remove unneeded empty conditions and preparation statements from expanders

Message ID AANLkTiniRtfq4Un2=xa9Aacy+3sPGqiDGwxvTKwhNKfZ@mail.gmail.com
State New
Headers show

Commit Message

Uros Bizjak Sept. 16, 2010, 8:35 a.m. UTC 
Hello!

2010-09-16  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md: Remove unneeded empty conditions and
	preparation statements from expanders.
	* config/i386/mmx.md: Ditto.
	* config/i386/sse.md: Ditto.

Tested on x86_64-pc-linux-gnu {,-m32}, committed to mainline.

Uros.
diff mbox

Patch

Index: i386.md
===================================================================
--- i386.md	(revision 164327)
+++ i386.md	(working copy)
@@ -979,9 +979,7 @@ 
 (define_expand "cmp<mode>_1"
   [(set (reg:CC FLAGS_REG)
 	(compare:CC (match_operand:SWI48 0 "nonimmediate_operand" "")
-		    (match_operand:SWI48 1 "<general_operand>" "")))]
-  ""
-  "")
+		    (match_operand:SWI48 1 "<general_operand>" "")))])
 
 (define_insn "*cmp<mode>_ccno_1"
   [(set (reg FLAGS_REG)
@@ -1066,9 +1064,7 @@ 
 	      (match_operand 0 "ext_register_operand" "")
 	      (const_int 8)
 	      (const_int 8)) 0)
-	  (match_operand:QI 1 "immediate_operand" "")))]
-  ""
-  "")
+	  (match_operand:QI 1 "immediate_operand" "")))])
 
 (define_insn "*cmpqi_ext_3_insn"
   [(set (reg FLAGS_REG)
@@ -2544,9 +2540,7 @@ 
   [(set (zero_extract:SWI48 (match_operand 0 "ext_register_operand" "")
 			    (const_int 8)
 			    (const_int 8))
-	(match_operand:SWI48 1 "nonmemory_operand" ""))]
-  ""
-  "")
+	(match_operand:SWI48 1 "nonmemory_operand" ""))])
 
 (define_insn "*mov<mode>_insv_1_rex64"
   [(set (zero_extract:SWI48x (match_operand 0 "ext_register_operand" "+Q")
@@ -3690,9 +3684,7 @@ 
   [(parallel
     [(set (match_operand:SWI24 0 "register_operand" "")
 	  (zero_extend:SWI24 (match_operand:QI 1 "nonimmediate_operand" "")))
-     (clobber (reg:CC FLAGS_REG))])]
-  ""
-  "")
+     (clobber (reg:CC FLAGS_REG))])])
 
 (define_insn "*zero_extendqi<mode>2_and"
   [(set (match_operand:SWI24 0 "register_operand" "=r,?&q")
@@ -4209,8 +4201,7 @@ 
 (define_expand "truncdfsf2_with_temp"
   [(parallel [(set (match_operand:SF 0 "" "")
 		   (float_truncate:SF (match_operand:DF 1 "" "")))
-	      (clobber (match_operand:SF 2 "" ""))])]
-  "")
+	      (clobber (match_operand:SF 2 "" ""))])])
 
 (define_insn "*truncdfsf_fast_mixed"
   [(set (match_operand:SF 0 "nonimmediate_operand"   "=fm,x")
@@ -4854,8 +4845,7 @@ 
 	(float:X87MODEF (match_operand:HI 1 "nonimmediate_operand" "")))]
   "TARGET_80387
    && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
-       || TARGET_MIX_SSE_I387)"
-  "")
+       || TARGET_MIX_SSE_I387)")
 
 ;; Pre-reload splitter to add memory clobber to the pattern.
 (define_insn_and_split "*floathi<mode>2_1"
@@ -6712,8 +6702,7 @@ 
 			(const_int 0)])
 		      (match_operand:SWI 2 "<general_operand>" ""))))
      (clobber (reg:CC FLAGS_REG))])]
-  "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)"
-  "")
+  "ix86_binary_operator_ok (<CODE>, <MODE>mode, operands)")
 
 (define_insn "*<plusminus_insn><mode>3_carry"
   [(set (match_operand:SWI 0 "nonimmediate_operand" "=<r>m,<r>")
@@ -6822,8 +6811,7 @@ 
 	(plusminus:XF
 	  (match_operand:XF 1 "register_operand" "")
 	  (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
-  "")
+  "TARGET_80387")
 
 (define_expand "<plusminus_insn><mode>3"
   [(set (match_operand:MODEF 0 "register_operand" "")
@@ -6831,8 +6819,7 @@ 
 	  (match_operand:MODEF 1 "register_operand" "")
 	  (match_operand:MODEF 2 "nonimmediate_operand" "")))]
   "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
-    || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
-  "")
+    || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)")
 
 ;; Multiply instructions
 
@@ -6841,9 +6828,7 @@ 
 		   (mult:SWIM248
 		     (match_operand:SWIM248 1 "register_operand" "")
 		     (match_operand:SWIM248 2 "<general_operand>" "")))
-	      (clobber (reg:CC FLAGS_REG))])]
-  ""
-  "")
+	      (clobber (reg:CC FLAGS_REG))])])
 
 (define_expand "mulqi3"
   [(parallel [(set (match_operand:QI 0 "register_operand" "")
@@ -6851,8 +6836,7 @@ 
 		     (match_operand:QI 1 "register_operand" "")
 		     (match_operand:QI 2 "nonimmediate_operand" "")))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "TARGET_QIMODE_MATH"
-  "")
+  "TARGET_QIMODE_MATH")
 
 ;; On AMDFAM10
 ;; IMUL reg32/64, reg32/64, imm8 	Direct
@@ -6982,9 +6966,7 @@ 
 		       (match_operand:DWIH 1 "nonimmediate_operand" ""))
 		     (any_extend:<DWI>
 		       (match_operand:DWIH 2 "register_operand" ""))))
-	      (clobber (reg:CC FLAGS_REG))])]
-  ""
-  "")
+	      (clobber (reg:CC FLAGS_REG))])])
 
 (define_expand "<u>mulqihi3"
   [(parallel [(set (match_operand:HI 0 "register_operand" "")
@@ -6994,8 +6976,7 @@ 
 		     (any_extend:HI
 		       (match_operand:QI 2 "register_operand" ""))))
 	      (clobber (reg:CC FLAGS_REG))])]
-  "TARGET_QIMODE_MATH"
-  "")
+  "TARGET_QIMODE_MATH")
 
 (define_insn "*<u>mul<mode><dwi>3_1"
   [(set (match_operand:<DWI> 0 "register_operand" "=A")
@@ -7127,16 +7108,14 @@ 
   [(set (match_operand:XF 0 "register_operand" "")
 	(mult:XF (match_operand:XF 1 "register_operand" "")
 		 (match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
-  "")
+  "TARGET_80387")
 
 (define_expand "mul<mode>3"
   [(set (match_operand:MODEF 0 "register_operand" "")
 	(mult:MODEF (match_operand:MODEF 1 "register_operand" "")
 		    (match_operand:MODEF 2 "nonimmediate_operand" "")))]
   "(TARGET_80387 && X87_ENABLE_ARITH (<MODE>mode))
-    || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)"
-  "")
+    || (SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)")
 
 ;; Divide instructions
 
@@ -7146,16 +7125,14 @@ 
   [(set (match_operand:XF 0 "register_operand" "")
 	(div:XF (match_operand:XF 1 "register_operand" "")
 		(match_operand:XF 2 "register_operand" "")))]
-  "TARGET_80387"
-  "")
+  "TARGET_80387")
 
 (define_expand "divdf3"
   [(set (match_operand:DF 0 "register_operand" "")
  	(div:DF (match_operand:DF 1 "register_operand" "")
  		(match_operand:DF 2 "nonimmediate_operand" "")))]
    "(TARGET_80387 && X87_ENABLE_ARITH (DFmode))
-    || (TARGET_SSE2 && TARGET_SSE_MATH)"
-   "")
+    || (TARGET_SSE2 && TARGET_SSE_MATH)")
 
 (define_expand "divsf3"
   [(set (match_operand:SF 0 "register_operand" "")
@@ -7302,9 +7279,7 @@ 
 		     (match_operand:SWIM248 2 "nonimmediate_operand" "")))
 	      (set (match_operand:SWIM248 3 "register_operand" "")
 		   (mod:SWIM248 (match_dup 1) (match_dup 2)))
-	      (clobber (reg:CC FLAGS_REG))])]
-  ""
-  "")
+	      (clobber (reg:CC FLAGS_REG))])])
 
 (define_insn_and_split "*divmod<mode>4"
   [(set (match_operand:SWIM248 0 "register_operand" "=a")
@@ -7361,9 +7336,7 @@ 
 		     (match_operand:SWIM248 2 "nonimmediate_operand" "")))
 	      (set (match_operand:SWIM248 3 "register_operand" "")
 		   (umod:SWIM248 (match_dup 1) (match_dup 2)))
-	      (clobber (reg:CC FLAGS_REG))])]
-  ""
-  "")
+	      (clobber (reg:CC FLAGS_REG))])])
 
 (define_insn_and_split "*udivmod<mode>4"
   [(set (match_operand:SWIM248 0 "register_operand" "=a")
@@ -7428,17 +7401,13 @@ 
 	(compare:CCNO
 	  (and:SI (match_operand:SI 0 "nonimmediate_operand" "")
 		  (match_operand:SI 1 "nonmemory_operand" ""))
-	  (const_int 0)))]
-  ""
-  "")
+	  (const_int 0)))])
 
 (define_expand "testqi_ccz_1"
   [(set (reg:CCZ FLAGS_REG)
         (compare:CCZ (and:QI (match_operand:QI 0 "nonimmediate_operand" "")
 			     (match_operand:QI 1 "nonmemory_operand" ""))
-		 (const_int 0)))]
-  ""
-  "")
+		 (const_int 0)))])
 
 (define_insn "*testdi_1"
   [(set (reg FLAGS_REG)
@@ -7508,9 +7477,7 @@ 
 	      (const_int 8)
 	      (const_int 8))
 	    (match_operand 1 "const_int_operand" ""))
-	  (const_int 0)))]
-  ""
-  "")
+	  (const_int 0)))])
 
 (define_insn "*testqi_ext_0"
   [(set (reg FLAGS_REG)
@@ -8440,9 +8407,7 @@ 
 	     (match_dup 1)
 	     (const_int 8)
 	     (const_int 8))
-	    (match_dup 2)))])]
-  ""
-  "")
+	    (match_dup 2)))])])
 
 (define_insn "*xorqi_cc_ext_1_rex64"
   [(set (reg FLAGS_REG)
@@ -12046,8 +12011,7 @@ 
 			      UNSPEC_TLS_GD))
 	      (clobber (match_dup 4))
 	      (clobber (match_dup 5))
-	      (clobber (reg:CC FLAGS_REG))])]
-  "")
+	      (clobber (reg:CC FLAGS_REG))])])
 
 ;; Segment register for the thread base ptr load
 (define_mode_attr tp_seg [(SI "gs") (DI "fs")])
@@ -13153,8 +13117,7 @@ 
 			      UNSPEC_FPATAN))
 	      (clobber (match_scratch:XF 3 ""))])]
   "TARGET_USE_FANCY_MATH_387
-   && flag_unsafe_math_optimizations"
-  "")
+   && flag_unsafe_math_optimizations")
 
 (define_expand "atan2<mode>3"
   [(use (match_operand:MODEF 0 "register_operand" ""))
@@ -13505,9 +13468,7 @@ 
 		   (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
-{
-  operands[2] = gen_reg_rtx (XFmode);
-})
+  "operands[2] = gen_reg_rtx (XFmode);")
 
 (define_expand "logb<mode>2"
   [(use (match_operand:MODEF 0 "register_operand" ""))
@@ -13891,9 +13852,7 @@ 
 		   (unspec:XF [(match_dup 1)] UNSPEC_XTRACT_EXP))])]
   "TARGET_USE_FANCY_MATH_387
    && flag_unsafe_math_optimizations"
-{
-  operands[2] = gen_reg_rtx (XFmode);
-})
+  "operands[2] = gen_reg_rtx (XFmode);")
 
 (define_expand "significand<mode>2"
   [(use (match_operand:MODEF 0 "register_operand" ""))
@@ -14106,16 +14065,14 @@ 
   [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
      (unspec:X87MODEI [(match_operand:XF 1 "register_operand" "")]
 		      UNSPEC_FIST))]
-  "TARGET_USE_FANCY_MATH_387"
-  "")
+  "TARGET_USE_FANCY_MATH_387")
 
 (define_expand "lrint<MODEF:mode><SSEMODEI24:mode>2"
   [(set (match_operand:SSEMODEI24 0 "nonimmediate_operand" "")
      (unspec:SSEMODEI24 [(match_operand:MODEF 1 "register_operand" "")]
 			UNSPEC_FIX_NOTRUNC))]
   "SSE_FLOAT_MODE_P (<MODEF:MODE>mode) && TARGET_SSE_MATH
-   && ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)"
-  "")
+   && ((<SSEMODEI24:MODE>mode != DImode) || TARGET_64BIT)")
 
 (define_expand "lround<MODEF:mode><SSEMODEI24:mode>2"
   [(match_operand:SSEMODEI24 0 "nonimmediate_operand" "")
@@ -14373,8 +14330,7 @@ 
 	      (clobber (reg:CC FLAGS_REG))])]
   "TARGET_USE_FANCY_MATH_387
    && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-  "")
+   && flag_unsafe_math_optimizations")
 
 (define_expand "lfloor<MODEF:mode><SWI48:mode>2"
   [(match_operand:SWI48 0 "nonimmediate_operand" "")
@@ -14631,8 +14587,7 @@ 
 	      (clobber (reg:CC FLAGS_REG))])]
   "TARGET_USE_FANCY_MATH_387
    && (!TARGET_SSE_MATH || TARGET_MIX_SSE_I387)
-   && flag_unsafe_math_optimizations"
-  "")
+   && flag_unsafe_math_optimizations")
 
 (define_expand "lceil<MODEF:mode><SWI48:mode>2"
   [(match_operand:SWI48 0 "nonimmediate_operand" "")
@@ -14782,7 +14737,6 @@ 
    && flag_unsafe_math_optimizations"
 {
   emit_insn (gen_frndintxf2_mask_pm (operands[0], operands[1]));
-
   DONE;
 })
 
@@ -15803,9 +15757,7 @@ 
 	      (const_int 0)])
 	    (const_int -1)
 	    (const_int 0)))
-     (clobber (reg:CC FLAGS_REG))])]
-  ""
-  "")
+     (clobber (reg:CC FLAGS_REG))])])
 
 (define_insn "*x86_mov<mode>cc_0_m1"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
@@ -17617,8 +17569,7 @@ 
 (define_expand "lwp_llwpcb"
   [(unspec_volatile [(match_operand 0 "register_operand" "r")]
 		    UNSPECV_LLWP_INTRINSIC)]
-  "TARGET_LWP"
-  "")
+  "TARGET_LWP")
 
 (define_insn "*lwp_llwpcb<mode>1"
   [(unspec_volatile [(match_operand:P 0 "register_operand" "r")]
@@ -17679,8 +17630,7 @@ 
 			     UNSPECV_LWPINS_INTRINSIC))
    (set (match_operand:QI 0 "nonimmediate_operand" "=qm")
 	(eq:QI (reg:CCC FLAGS_REG) (const_int 0)))]
-  "TARGET_LWP"
-  "")
+  "TARGET_LWP")
 
 (define_insn "*lwp_lwpins<mode>3_1"
   [(set (reg:CCC FLAGS_REG)
Index: mmx.md
===================================================================
--- mmx.md	(revision 164327)
+++ mmx.md	(working copy)
@@ -341,15 +341,13 @@ 
   [(set (match_operand:V2SF 0 "register_operand" "")
         (minus:V2SF (match_operand:V2SF 1 "register_operand" "")
 		    (match_operand:V2SF 2 "nonimmediate_operand" "")))]
-  "TARGET_3DNOW"
-  "")
+  "TARGET_3DNOW")
 
 (define_expand "mmx_subrv2sf3"
   [(set (match_operand:V2SF 0 "register_operand" "")
         (minus:V2SF (match_operand:V2SF 2 "register_operand" "")
 		    (match_operand:V2SF 1 "nonimmediate_operand" "")))]
-  "TARGET_3DNOW"
-  "")
+  "TARGET_3DNOW")
 
 (define_insn "*mmx_subv2sf3"
   [(set (match_operand:V2SF 0 "register_operand" "=y,y")
@@ -1623,8 +1621,7 @@ 
 		      (match_operand:V8QI 2 "register_operand" "")
 		      (match_dup 0)]
 		     UNSPEC_MASKMOV))]
-  "TARGET_SSE || TARGET_3DNOW_A"
-  "")
+  "TARGET_SSE || TARGET_3DNOW_A")
 
 (define_insn "*mmx_maskmovq"
   [(set (mem:V8QI (match_operand:SI 0 "register_operand" "D"))
Index: sse.md
===================================================================
--- sse.md	(revision 164327)
+++ sse.md	(working copy)
@@ -508,30 +508,26 @@ 
 	(unspec:SSEMODEF2P
 	  [(match_operand:SSEMODEF2P 1 "register_operand" "")]
 	  UNSPEC_MOVNT))]
-  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)"
-  "")
+  "SSE_VEC_FLOAT_MODE_P (<MODE>mode)")
 
 (define_expand "storent<mode>"
   [(set (match_operand:MODEF 0 "memory_operand" "")
 	(unspec:MODEF
 	  [(match_operand:MODEF 1 "register_operand" "")]
 	  UNSPEC_MOVNT))]
-  "TARGET_SSE4A"
-  "")
+  "TARGET_SSE4A")
 
 (define_expand "storentv2di"
   [(set (match_operand:V2DI 0 "memory_operand" "")
 	(unspec:V2DI [(match_operand:V2DI 1 "register_operand" "")]
 		     UNSPEC_MOVNT))]
-  "TARGET_SSE2"
-  "")
+  "TARGET_SSE2")
 
 (define_expand "storentsi"
   [(set (match_operand:SI 0 "memory_operand" "")
 	(unspec:SI [(match_operand:SI 1 "register_operand" "")]
 		   UNSPEC_MOVNT))]
-  "TARGET_SSE2"
-  "")
+  "TARGET_SSE2")
 
 ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 ;;
@@ -734,8 +730,7 @@ 
   [(set (match_operand:V2DF 0 "register_operand" "")
 	(div:V2DF (match_operand:V2DF 1 "register_operand" "")
 		  (match_operand:V2DF 2 "nonimmediate_operand" "")))]
-  "TARGET_SSE2"
-  "")
+  "TARGET_SSE2")
 
 (define_insn "*avx_div<mode>3"
   [(set (match_operand:SSEMODEF2P 0 "register_operand" "=x")
@@ -3107,9 +3102,7 @@ 
        (match_dup 2)
        (parallel [(const_int 0) (const_int 1)]))))]
  "TARGET_SSE2"
-{
- operands[2] = gen_reg_rtx (V4SFmode);
-})
+  "operands[2] = gen_reg_rtx (V4SFmode);")
 
 (define_expand "vec_unpacks_lo_v4sf"
   [(set (match_operand:V2DF 0 "register_operand" "")
@@ -4467,8 +4460,7 @@ 
 	    (match_dup 1))
 	  (parallel [(const_int 0) (const_int 4)
 		     (const_int 2) (const_int 6)])))]
-  "TARGET_AVX"
-  "")
+  "TARGET_AVX")
 
 (define_expand "avx_unpcklpd256"
   [(set (match_operand:V4DF 0 "register_operand" "")
@@ -4478,8 +4470,7 @@ 
 	    (match_operand:V4DF 2 "nonimmediate_operand" ""))
 	  (parallel [(const_int 0) (const_int 4)
 		     (const_int 2) (const_int 6)])))]
-  "TARGET_AVX"
-  "")
+  "TARGET_AVX")
 
 (define_insn "*avx_unpcklpd256"
   [(set (match_operand:V4DF 0 "register_operand"         "=x,x")
@@ -4813,9 +4804,7 @@ 
 	  (parallel [(const_int 1)])))]
   "TARGET_SSE2 && reload_completed"
   [(set (match_dup 0) (match_dup 1))]
-{
-  operands[1] = adjust_address (operands[1], DFmode, 8);
-})
+  "operands[1] = adjust_address (operands[1], DFmode, 8);")
 
 ;; Avoid combining registers from different units in a single alternative,
 ;; see comment above inline_secondary_memory_needed function in i386.c
@@ -4910,9 +4899,7 @@ 
 	  (match_operand:DF 1 "register_operand" "")))]
   "TARGET_SSE2 && reload_completed"
   [(set (match_dup 0) (match_dup 1))]
-{
-  operands[0] = adjust_address (operands[0], DFmode, 8);
-})
+  "operands[0] = adjust_address (operands[0], DFmode, 8);")
 
 (define_expand "sse2_loadlpd_exp"
   [(set (match_operand:V2DF 0 "nonimmediate_operand" "")
@@ -4975,9 +4962,7 @@ 
 	  (vec_select:DF (match_dup 0) (parallel [(const_int 1)]))))]
   "TARGET_SSE2 && reload_completed"
   [(set (match_dup 0) (match_dup 1))]
-{
-  operands[0] = adjust_address (operands[0], DFmode, 8);
-})
+  "operands[0] = adjust_address (operands[0], DFmode, 8);")
 
 ;; Not sure these two are ever used, but it doesn't hurt to have
 ;; them. -aoliva
@@ -7313,9 +7298,7 @@ 
        || MEM_P (operands [0])
        || !GENERAL_REGNO_P (true_regnum (operands [0])))"
   [(set (match_dup 0) (match_dup 1))]
-{
-  operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]));
-})
+  "operands[1] = gen_rtx_REG (SImode, REGNO (operands[1]));")
 
 (define_insn_and_split "*vec_ext_v4si_mem"
   [(set (match_operand:SI 0 "register_operand" "=r")
@@ -7338,8 +7321,7 @@ 
 	(vec_select:DI
 	  (match_operand:V2DI 1 "register_operand" "")
 	  (parallel [(const_int 0)])))]
-  "TARGET_SSE"
-  "")
+  "TARGET_SSE")
 
 (define_insn "*sse2_storeq_rex64"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=mx,*r,r")
@@ -7374,9 +7356,7 @@ 
        || MEM_P (operands [0])
        || !GENERAL_REGNO_P (true_regnum (operands [0])))"
   [(set (match_dup 0) (match_dup 1))]
-{
-  operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));
-})
+  "operands[1] = gen_rtx_REG (DImode, REGNO (operands[1]));")
 
 (define_insn "*vec_extractv2di_1_rex64_avx"
   [(set (match_operand:DI 0 "nonimmediate_operand" "=m,x,x,r")
@@ -8055,8 +8035,7 @@ 
 		       (match_operand:V16QI 2 "register_operand" "")
 		       (match_dup 0)]
 		      UNSPEC_MASKMOV))]
-  "TARGET_SSE2"
-  "")
+  "TARGET_SSE2")
 
 (define_insn "*sse2_maskmovdqu"
   [(set (mem:V16QI (match_operand:SI 0 "register_operand" "D"))
@@ -11508,9 +11487,7 @@ 
   "&& reload_completed && REG_P (operands[1])"
   [(set (match_dup 2) (vec_duplicate:<avxhalfvecmode> (match_dup 1)))
    (set (match_dup 0) (vec_concat:AVX256MODE24P (match_dup 2) (match_dup 2)))]
-{
-  operands[2] = gen_rtx_REG (<avxhalfvecmode>mode, REGNO (operands[0]));
-}
+  "operands[2] = gen_rtx_REG (<avxhalfvecmode>mode, REGNO (operands[0]));"
   [(set_attr "type" "ssemov")
    (set_attr "prefix_extra" "1")
    (set_attr "prefix" "vex")