Patchwork [RX] Minor patches

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Submitter DJ Delorie
Date Sept. 15, 2010, 3:41 a.m.
Message ID <201009150341.o8F3fPc4020423@greed.delorie.com>
Download mbox | patch
Permalink /patch/64772/
State New
Headers show

Comments

DJ Delorie - Sept. 15, 2010, 3:41 a.m.
> On 08/27/2010 11:45 AM, DJ Delorie wrote:
> > Should the user-level error() be moved to rx_expand_builtin_mvtipl()
> > instead?
> 
> Yes please.

New patch...  includes some minor patches from before also, and made
some of the builtins volatile.  Cleaned up the relevent test case and
added one to check for the error cases as well.
Richard Henderson - Sept. 15, 2010, 3:39 p.m.
On 09/14/2010 08:41 PM, DJ Delorie wrote:
>> On 08/27/2010 11:45 AM, DJ Delorie wrote:
>>> Should the user-level error() be moved to rx_expand_builtin_mvtipl()
>>> instead?
>>
>> Yes please.
> 
> New patch...  includes some minor patches from before also, and made
> some of the builtins volatile.  Cleaned up the relevent test case and
> added one to check for the error cases as well.

Better, thanks.


r~

Patch

Index: config/rx/rx.md
===================================================================
--- config/rx/rx.md	(revision 164265)
+++ config/rx/rx.md	(working copy)
@@ -1366,23 +1366,23 @@ 
 		   (ashift:SI (const_int 1)
 			      (match_dup 1))))]
   ""
 )
 
 (define_insn "bitclr"
-  [(set:SI (match_operand:SI 0 "register_operand" "+r")
+  [(set:SI (match_operand:SI 0 "register_operand" "=r")
 	   (and:SI (match_operand:SI 1 "register_operand" "0")
 		   (not:SI (ashift:SI (const_int 1)
 				      (match_operand:SI 2 "nonmemory_operand" "ri")))))]
   ""
   "bclr\t%2, %0"
   [(set_attr "length" "3")]
 )
 
 (define_insn "bitclr_in_memory"
-  [(set:QI (match_operand:QI 0 "memory_operand" "+m")
+  [(set:QI (match_operand:QI 0 "memory_operand" "=m")
 	   (and:QI (match_operand:QI 1 "memory_operand" "0")
 		   (not:QI (ashift:QI (const_int 1)
 				      (match_operand:QI 2 "nonmemory_operand" "ri")))))]
   ""
   "bclr\t%2, %0.B"
   [(set_attr "length" "3")
@@ -1800,43 +1800,43 @@ 
 )
 
 ;;---------- Control Registers ------------------------
 
 ;; Clear Processor Status Word
 (define_insn "clrpsw"
-  [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")]
+  [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
 	      UNSPEC_BUILTIN_CLRPSW)
    (clobber (reg:CC CC_REG))]
   ""
   "clrpsw\t%F0"
   [(set_attr "length" "2")]
 )
 
 ;; Set Processor Status Word
 (define_insn "setpsw"
-  [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i")]
+  [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i")]
 	      UNSPEC_BUILTIN_SETPSW)
    (clobber (reg:CC CC_REG))]
   ""
   "setpsw\t%F0"
   [(set_attr "length" "2")]
 )
 
 ;; Move from control register
 (define_insn "mvfc"
   [(set (match_operand:SI             0 "register_operand" "=r")
-	(unspec:SI [(match_operand:SI 1 "immediate_operand" "i")]
+	(unspec_volatile:SI [(match_operand:SI 1 "immediate_operand" "i")]
 		   UNSPEC_BUILTIN_MVFC))]
   ""
   "mvfc\t%C1, %0"
   [(set_attr "length" "3")]
 )
 
 ;; Move to control register
 (define_insn "mvtc"
-  [(unspec:SI [(match_operand:SI 0 "immediate_operand" "i,i")
+  [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "i,i")
 	       (match_operand:SI 1 "nonmemory_operand" "r,i")]
 	      UNSPEC_BUILTIN_MVTC)]
   ""
   "mvtc\t%1, %C0"
   [(set_attr "length" "3,7")]
   ;; Ignore possible clobbering of the comparison flags in the
@@ -1845,13 +1845,13 @@ 
   ;; the possibility of this instruction being placed in between
   ;; them.
 )
 
 ;; Move to interrupt priority level
 (define_insn "mvtipl"
-  [(unspec:SI [(match_operand:SI 0 "immediate_operand" "Uint04")]
+  [(unspec_volatile:SI [(match_operand:SI 0 "immediate_operand" "Uint04")]
 	      UNSPEC_BUILTIN_MVTIPL)]
   ""
   "mvtipl\t%0"
   [(set_attr "length" "3")]
 )
 
Index: config/rx/rx.c
===================================================================
--- config/rx/rx.c	(revision 164265)
+++ config/rx/rx.c	(working copy)
@@ -1902,13 +1902,13 @@  static rtx
 rx_expand_builtin_mvtipl (rtx arg)
 {
   /* The RX610 does not support the MVTIPL instruction.  */
   if (rx_cpu_type == RX610)
     return NULL_RTX;
 
-  if (! CONST_INT_P (arg) || ! IN_RANGE (arg, 0, (1 << 4) - 1))
+  if (! CONST_INT_P (arg) || ! IN_RANGE (INTVAL (arg), 0, (1 << 4) - 1))
     return NULL_RTX;
 
   emit_insn (gen_mvtipl (arg));
 
   return NULL_RTX;
 }
@@ -1971,12 +1971,37 @@  rx_expand_builtin_round (rtx arg, rtx ta
 
   emit_insn (gen_lrintsf2 (target, arg));
 
   return target;
 }
 
+static int
+valid_psw_flag (rtx op, char *which)
+{
+  static int mvtc_inform_done = 0;
+
+  if (GET_CODE (op) == CONST_INT)
+    switch (INTVAL (op))
+      {
+      case 0: case 'c': case 'C':
+      case 1: case 'z': case 'Z':
+      case 2: case 's': case 'S':
+      case 3: case 'o': case 'O':
+      case 8: case 'i': case 'I':
+      case 9: case 'u': case 'U':
+	return 1;
+      }
+
+  error ("__builtin_rx_%s takes 'C', 'Z', 'S', 'O', 'I', or 'U'", which);
+  if (!mvtc_inform_done)
+    error ("use __builtin_rx_mvtc (0, ... ) to write arbitrary values to PSW");
+  mvtc_inform_done = 1;
+
+  return 0;
+}
+
 static rtx
 rx_expand_builtin (tree exp,
 		   rtx target,
 		   rtx subtarget ATTRIBUTE_UNUSED,
 		   enum machine_mode mode ATTRIBUTE_UNUSED,
 		   int ignore ATTRIBUTE_UNUSED)
@@ -1986,16 +2011,20 @@  rx_expand_builtin (tree exp,
   rtx  op     = arg ? expand_normal (arg) : NULL_RTX;
   unsigned int fcode = DECL_FUNCTION_CODE (fndecl);
 
   switch (fcode)
     {
     case RX_BUILTIN_BRK:     emit_insn (gen_brk ()); return NULL_RTX;
-    case RX_BUILTIN_CLRPSW:  return rx_expand_void_builtin_1_arg
-	(op, gen_clrpsw, false);
-    case RX_BUILTIN_SETPSW:  return rx_expand_void_builtin_1_arg
-	(op, gen_setpsw, false);
+    case RX_BUILTIN_CLRPSW:
+      if (!valid_psw_flag (op, "clrpsw"))
+	return NULL_RTX;
+      return rx_expand_void_builtin_1_arg (op, gen_clrpsw, false);
+    case RX_BUILTIN_SETPSW:
+      if (!valid_psw_flag (op, "setpsw"))
+	return NULL_RTX;
+      return rx_expand_void_builtin_1_arg (op, gen_setpsw, false);
     case RX_BUILTIN_INT:     return rx_expand_void_builtin_1_arg
 	(op, gen_int, false);
     case RX_BUILTIN_MACHI:   return rx_expand_builtin_mac (exp, gen_machi);
     case RX_BUILTIN_MACLO:   return rx_expand_builtin_mac (exp, gen_maclo);
     case RX_BUILTIN_MULHI:   return rx_expand_builtin_mac (exp, gen_mulhi);
     case RX_BUILTIN_MULLO:   return rx_expand_builtin_mac (exp, gen_mullo);
Index: testsuite/gcc.target/rx/builtins.c
===================================================================
--- testsuite/gcc.target/rx/builtins.c	(revision 164265)
+++ testsuite/gcc.target/rx/builtins.c	(working copy)
@@ -29,19 +29,12 @@  int
 saturate_add (int arg1, int arg2)
 {
   arg1 += arg2;
   return __builtin_rx_sat (arg1);
 }
 
-int
-exchange (int arg1, int arg2)
-{
-  arg1 = __builtin_rx_xchg (arg2);
-  return arg1;
-}
-
 long
 multiply_and_accumulate (long arg1, long arg2, long arg3)
 {
   __builtin_rx_mvtaclo (0);
   __builtin_rx_mvtachi (0);
 
@@ -164,8 +157,56 @@  rmpa (int * multiplicand, int * multipli
   __builtin_rx_rmpa ();
 }
 
 void
 set_interrupts (void)
 {
-  __builtin_mvtipl (3);
+  __builtin_rx_mvtipl (3);
+}
+
+set_psw (int i)
+{
+  /* Thse are all valid */
+  __builtin_rx_setpsw('C');
+  __builtin_rx_setpsw('Z');
+  __builtin_rx_setpsw('S');
+  __builtin_rx_setpsw('O');
+  __builtin_rx_setpsw('I');
+  __builtin_rx_setpsw('U');
+  __builtin_rx_setpsw('c');
+  __builtin_rx_setpsw('z');
+  __builtin_rx_setpsw('s');
+  __builtin_rx_setpsw('o');
+  __builtin_rx_setpsw('i');
+  __builtin_rx_setpsw('u');
+  __builtin_rx_setpsw(0);
+  __builtin_rx_setpsw(1);
+  __builtin_rx_setpsw(2);
+  __builtin_rx_setpsw(3);
+  __builtin_rx_setpsw(8);
+  __builtin_rx_setpsw(9);
+  __builtin_rx_mvtc (0, i);
+}
+
+clear_psw (int i)
+{
+  /* Thse are all valid */
+  __builtin_rx_clrpsw('C');
+  __builtin_rx_clrpsw('Z');
+  __builtin_rx_clrpsw('S');
+  __builtin_rx_clrpsw('O');
+  __builtin_rx_clrpsw('I');
+  __builtin_rx_clrpsw('U');
+  __builtin_rx_clrpsw('c');
+  __builtin_rx_clrpsw('z');
+  __builtin_rx_clrpsw('s');
+  __builtin_rx_clrpsw('o');
+  __builtin_rx_clrpsw('i');
+  __builtin_rx_clrpsw('u');
+  __builtin_rx_clrpsw(0);
+  __builtin_rx_clrpsw(1);
+  __builtin_rx_clrpsw(2);
+  __builtin_rx_clrpsw(3);
+  __builtin_rx_clrpsw(8);
+  __builtin_rx_clrpsw(9);
+  __builtin_rx_mvtc (0, i);
 }