| Message ID | 4C8F4287.1080308@codesourcery.com |
|---|---|
| State | New |
| Headers | show |
> + /* Disable -fsched-interblock for Cortex-M4. */ > + if (arm_selected_tune->core == cortexm4) > + flag_schedule_interblock = 0; Also, this needs a better comment. The current one adds no useful information. Based on your reply to Steven's questions maybe: "Interblock scheduling can move instructions into more frequently executed blocks in a loop. Disable this on cores with extremely short/simple pipelines." I'd be amazed if the Cortex-M4 is the only CPU that benefits from this. My guess is the same is true for the Cortex-M3, and maybe even all the ARM7/ARM9 cores. I suggest using Richard's new tune_params infrastructure. Ideally the interblock scheduler would have a knob to prevent moving instructions into warmer (ore frequently executed) blocks. Assuming this doesn't exist (I have not checked) this seems a reasonable workaround. Paul
On Mon, Sep 20, 2010 at 11:22 AM, Paul Brook <paul@codesourcery.com> wrote: > Ideally the interblock scheduler would have a knob to prevent moving > instructions into warmer (ore frequently executed) blocks. Right. I can almost not believe that the scheduler would do something like that, and I am curious about the test case. It almost sounds as if there is another, deeper issue, such as failing somewhere to update bb/edge execution counts or an error in branch prediction... Ciao! Steven
* config/arm/arm.c (arm_override_options): Disable -fsched-interblock for Cortex-M4. Index: config/arm/arm.c =================================================================== --- config/arm/arm.c (revision 164242) +++ config/arm/arm.c (working copy) @@ -1886,6 +1886,10 @@ arm_override_options (void) fix_cm3_ldrd = 0; } + /* Disable -fsched-interblock for Cortex-M4. */ + if (arm_selected_tune->core == cortexm4) + flag_schedule_interblock = 0; + if (TARGET_THUMB1 && flag_schedule_insns) { /* Don't warn since it's on by default in -O2. */