From patchwork Mon Sep 13 11:06:46 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Marcus Shawcroft X-Patchwork-Id: 64581 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id AB3F9B70A3 for ; Mon, 13 Sep 2010 21:07:09 +1000 (EST) Received: (qmail 8246 invoked by alias); 13 Sep 2010 11:07:06 -0000 Received: (qmail 8236 invoked by uid 22791); 13 Sep 2010 11:07:03 -0000 X-SWARE-Spam-Status: No, hits=-0.4 required=5.0 tests=AWL, BAYES_00, MSGID_MULTIPLE_AT, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from cam-admin0.cambridge.arm.com (HELO cam-admin0.cambridge.arm.com) (217.140.96.50) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 13 Sep 2010 11:06:54 +0000 Received: from cam-owa2.Emea.Arm.com (cam-owa2.emea.arm.com [10.1.105.18]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id o8DB4WF9024357 for ; Mon, 13 Sep 2010 12:04:32 +0100 (BST) Received: from e102573 ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 13 Sep 2010 12:06:49 +0100 From: "Marcus Shawcroft" To: References: In-Reply-To: Subject: [PATCH, ARM] Prevent inappropriate attempt to conditionalize inline synchronization sequences. Date: Mon, 13 Sep 2010 12:06:46 +0100 Message-ID: <000c01cb5333$c1ca76e0$455f64a0$@shawcroft@arm.com> MIME-Version: 1.0 x-cr-hashedpuzzle: AYpB AY4r AbOG CtXw EuYV FwW6 GpRF Hjgn IXRz IjBr ItqV Jm3I JsOv Jwk9 L8GL MdPH; 1; ZwBjAGMALQBwAGEAdABjAGgAZQBzAEAAZwBjAGMALgBnAG4AdQAuAG8AcgBnAA==; Sosha1_v1; 7; {AA658DF0-F8EE-4C8F-9415-08536ACBC65C}; bQBhAHIAYwB1AHMALgBzAGgAYQB3AGMAcgBvAGYAdABAAGEAcgBtAC4AYwBvAG0A; Mon, 13 Sep 2010 11:06:42 GMT; WwBQAEEAVABDAEgALAAgAEEAUgBNAF0AIABQAHIAZQB2AGUAbgB0ACAAaQBuAGEAcABwAHIAbwBwAHIAaQBhAHQAZQAgAGEAdAB0AGUAbQBwAHQAIAB0AG8AIABjAG8AbgBkAGkAdABpAG8AbgBhAGwAaQB6AGUAIABpAG4AbABpAG4AZQAgAHMAeQBuAGMAaAByAG8AbgBpAHoAYQB0AGkAbwBuACAAcwBlAHEAdQBlAG4AYwBlAHMALgA= x-cr-puzzleid: {AA658DF0-F8EE-4C8F-9415-08536ACBC65C} X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org All but one of the define_insn patterns for inline synchronization builtins have the conds attribute set to nocond. This incorrectly allows the instruction to be conditionalized. This patch adds a test case and fixes the issue. /Marcus 2010-09-13 Marcus Shawcroft * config/arm/arm.md: (define_attr "conds"): Update comment. * config/arm/sync.md (arm_sync_compare_and_swapsi): Change conds attribute to clob. (arm_sync_compare_and_swapsi): Likewise. (arm_sync_compare_and_swap): Likewise. (arm_sync_lock_test_and_setsi): Likewise. (arm_sync_lock_test_and_set): Likewise. (arm_sync_new_si): Likewise. (arm_sync_new_nandsi): Likewise. (arm_sync_new_): Likewise. (arm_sync_new_nand): Likewise. (arm_sync_old_si): Likewise. (arm_sync_old_nandsi): Likewise. (arm_sync_old_): Likewise. (arm_sync_old_nand): Likewise. 2010-09-13 Marcus Shawcroft * gcc.target/arm/sync-1.c: New. diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 9d7310b..6e64d38 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -419,10 +419,11 @@ ; CLOB means that the condition codes are altered in an undefined manner, if ; they are altered at all ; -; UNCONDITIONAL means the instions can not be conditionally executed. +; UNCONDITIONAL means the instruction can not be conditionally executed and +; that the instruction does not use or alter the condition codes. ; -; NOCOND means that the condition codes are neither altered nor affect the -; output of this insn +; NOCOND means that the instruction does not use or alter the condition +; codes but can be converted into a conditionally exectuted instruction. (define_attr "conds" "use,set,clob,unconditional,nocond" (if_then_else diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md index f942d1f..4c4b4fa 100644 --- a/gcc/config/arm/sync.md +++ b/gcc/config/arm/sync.md @@ -300,7 +300,7 @@ (set_attr "sync_new_value" "3") (set_attr "sync_t1" "0") (set_attr "sync_t2" "4") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_compare_and_swap" @@ -327,7 +327,7 @@ (set_attr "sync_new_value" "3") (set_attr "sync_t1" "0") (set_attr "sync_t2" "4") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_lock_test_and_setsi" @@ -348,7 +348,7 @@ (set_attr "sync_new_value" "2") (set_attr "sync_t1" "0") (set_attr "sync_t2" "3") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_lock_test_and_set" @@ -369,7 +369,7 @@ (set_attr "sync_new_value" "2") (set_attr "sync_t1" "0") (set_attr "sync_t2" "3") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_new_si" @@ -394,7 +394,7 @@ (set_attr "sync_t1" "0") (set_attr "sync_t2" "3") (set_attr "sync_op" "") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_new_nandsi" @@ -419,7 +419,7 @@ (set_attr "sync_t1" "0") (set_attr "sync_t2" "3") (set_attr "sync_op" "nand") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_new_" @@ -445,7 +445,7 @@ (set_attr "sync_t1" "0") (set_attr "sync_t2" "3") (set_attr "sync_op" "") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_new_nand" @@ -472,7 +472,7 @@ (set_attr "sync_t1" "0") (set_attr "sync_t2" "3") (set_attr "sync_op" "nand") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_old_si" @@ -498,7 +498,7 @@ (set_attr "sync_t1" "3") (set_attr "sync_t2" "4") (set_attr "sync_op" "") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_old_nandsi" @@ -524,7 +524,7 @@ (set_attr "sync_t1" "3") (set_attr "sync_t2" "4") (set_attr "sync_op" "nand") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_old_" @@ -551,7 +551,7 @@ (set_attr "sync_t1" "3") (set_attr "sync_t2" "4") (set_attr "sync_op" "") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "arm_sync_old_nand" @@ -578,7 +578,7 @@ (set_attr "sync_t1" "3") (set_attr "sync_t2" "4") (set_attr "sync_op" "nand") - (set_attr "conds" "nocond") + (set_attr "conds" "clob") (set_attr "predicable" "no")]) (define_insn "*memory_barrier" diff --git a/gcc/testsuite/gcc.target/arm/sync-1.c b/gcc/testsuite/gcc.target/arm/sync-1.c new file mode 100644 index 0000000..ad85a04 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/sync-1.c @@ -0,0 +1,25 @@ +/* { dg-do run } */ +/* { dg-options "-O2 -march=armv7-a" } */ + +volatile int mem; + +int +bar (int x, int y) +{ + if (x) + __sync_fetch_and_add(&mem, y); + return 0; +} + +extern void abort (void); + +int +main (int argc, char *argv[]) +{ + mem = 0; + bar (0, 1); + bar (1, 1); + if (mem != 1) + abort (); + return 0; +}