From patchwork Sun Sep 12 19:59:17 2010
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Subject: Fix earlyclobbers on some arm.md DImode shifts
Date: Sun, 12 Sep 2010 09:59:17 -0000
From: Bernd Schmidt <bernds@codesourcery.com>
X-Patchwork-Id: 64562
Message-Id: <4C8D3115.5030804@codesourcery.com>
To: GCC Patches <gcc-patches@gcc.gnu.org>
Cc: Chung-Lin Tang <cltang@codesourcery.com>

Chung-Lin Tang discovered a testsuite failure on ARM with our internal 
tree after a few backports were applied.  execute/920501-6.c fails to 
terminate.

The problematic code generation change is

          movs    r7, r7, lsr #1 |         movs    r6, r7, lsr #1
          mov     r6, r6, rrx    |         mov     r5, r6, rrx

The cause is revision 154181, which switched alternatives in some insn 
patterns, but left the earlyclobbers in place - so they apply to the 
wrong alternative.

I tested the following patch against mainline with my usual qemu 
arm-linux setup.  Chung-Lin verified that it fixes the failure in our 
tree.  Committed as obvious.


Bernd


Index: ChangeLog
===================================================================
--- ChangeLog	(revision 164231)
+++ ChangeLog	(working copy)
@@ -1,3 +1,8 @@
+2010-09-12  Bernd Schmidt  <bernds@codesourcery.com>
+
+	* config/arm/arm.md (arm_ashldi3_1bit, arm_ashrdi3_1bit,
+	arm_lshrdi3_1bit): Put earlyclobber on the right alternative.
+
 2010-09-10  Jan Hubicka  <jh@suse.cz>
 
 	* tree-ssa-ccp.c (fold_const_aggregate_ref): Do not check STATIC flag.
Index: config/arm/arm.md
===================================================================
--- config/arm/arm.md	(revision 163935)
+++ config/arm/arm.md	(working copy)
@@ -3322,7 +3322,7 @@ (define_expand "ashldi3"
 )
 
 (define_insn "arm_ashldi3_1bit"
-  [(set (match_operand:DI            0 "s_register_operand" "=&r,r")
+  [(set (match_operand:DI            0 "s_register_operand" "=r,&r")
         (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r")
                    (const_int 1)))
    (clobber (reg:CC CC_REGNUM))]
@@ -3381,7 +3381,7 @@ (define_expand "ashrdi3"
 )
 
 (define_insn "arm_ashrdi3_1bit"
-  [(set (match_operand:DI              0 "s_register_operand" "=&r,r")
+  [(set (match_operand:DI              0 "s_register_operand" "=r,&r")
         (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
                      (const_int 1)))
    (clobber (reg:CC CC_REGNUM))]
@@ -3438,7 +3438,7 @@ (define_expand "lshrdi3"
 )
 
 (define_insn "arm_lshrdi3_1bit"
-  [(set (match_operand:DI              0 "s_register_operand" "=&r,r")
+  [(set (match_operand:DI              0 "s_register_operand" "=r,&r")
         (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
                      (const_int 1)))
    (clobber (reg:CC CC_REGNUM))]