From patchwork Wed Jul 6 09:34:23 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xu Ziyuan X-Patchwork-Id: 645189 X-Patchwork-Delegate: sjg@chromium.org Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from theia.denx.de (theia.denx.de [85.214.87.163]) by ozlabs.org (Postfix) with ESMTP id 3rkwbM5sfNz9sBm for ; Wed, 6 Jul 2016 19:35:27 +1000 (AEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id B3BFF4A039; Wed, 6 Jul 2016 11:35:08 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id qXZiy6BDtOb0; Wed, 6 Jul 2016 11:35:08 +0200 (CEST) Received: from theia.denx.de (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 00CF74BA35; Wed, 6 Jul 2016 11:35:08 +0200 (CEST) Received: from localhost (localhost [127.0.0.1]) by theia.denx.de (Postfix) with ESMTP id 6858CA74E0 for ; Wed, 6 Jul 2016 11:35:05 +0200 (CEST) Received: from theia.denx.de ([127.0.0.1]) by localhost (theia.denx.de [127.0.0.1]) (amavisd-new, port 10024) with ESMTP id beZZ_CZ4pwZt for ; Wed, 6 Jul 2016 11:35:05 +0200 (CEST) X-policyd-weight: NOT_IN_SBL_XBL_SPAMHAUS=-1.5 NOT_IN_SPAMCOP=-1.5 NOT_IN_BL_NJABL=-1.5 (only DNSBL check requested) Received: from regular1.263xmail.com (regular1.263xmail.com [211.150.99.133]) by theia.denx.de (Postfix) with ESMTPS id 0D91C4BDBD for ; Wed, 6 Jul 2016 11:34:55 +0200 (CEST) Received: from xzy.xu?rock-chips.com (unknown [192.168.167.11]) by regular1.263xmail.com (Postfix) with SMTP id DD3139156; Wed, 6 Jul 2016 17:34:49 +0800 (CST) X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-ADDR-CHECKED: 0 Received: from localhost.localdomain (localhost.localdomain [127.0.0.1]) by smtp.263.net (Postfix) with ESMTP id 7E02E6367; Wed, 6 Jul 2016 17:34:40 +0800 (CST) X-RL-SENDER: xzy.xu@rock-chips.com X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: xzy.xu@rock-chips.com X-UNIQUE-TAG: X-ATTACHMENT-NUM: 0 X-SENDER: xzy.xu@rock-chips.com X-DNS-TYPE: 0 Received: from unknown (unknown [103.29.142.67]) by smtp.263.net (Postfix) whith SMTP id 183281L7LWX; Wed, 06 Jul 2016 17:34:49 +0800 (CST) From: Ziyuan Xu To: sjg@chromium.org, marex@denx.de Date: Wed, 6 Jul 2016 17:34:23 +0800 Message-Id: <1467797663-16276-5-git-send-email-xzy.xu@rock-chips.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1467797663-16276-1-git-send-email-xzy.xu@rock-chips.com> References: <1467797663-16276-1-git-send-email-xzy.xu@rock-chips.com> Cc: hl@rock-chips.com, frank.wang@rock-chips.com, u-boot@lists.denx.de, eddie.cai@rock-chips.com, william.wu@rock-chips.com Subject: [U-Boot] [PATCH v3 4/4] usb: dwc2: invalidate dcache before starting DMA X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.15 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" From: Xu Ziyuan Invalidate dcache before starting the DMA to ensure coherency. In case there are any dirty lines from the DMA buffer in the cache, subsequent cache-line replacements may corrupt the buffer in memory while the DMA is still going on. Cache-line replacement can happen if the CPU tries to bring some other memory locations into the cache while the DMA is going on. Signed-off-by: Ziyuan Xu Reviewed-by: Simon Glass --- Changes in v3: - New commit since v3 to fix the coherence issue between memory and cache Changes in v2: None drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c index 12f5c85..0d6d2fb 100644 --- a/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c +++ b/drivers/usb/gadget/dwc2_udc_otg_xfer_dma.c @@ -110,6 +110,9 @@ static int setdma_rx(struct dwc2_ep *ep, struct dwc2_request *req) ctrl = readl(®->out_endp[ep_num].doepctl); + invalidate_dcache_range((unsigned long) ep->dma_buf, + (unsigned long) ep->dma_buf + ep->len); + writel((unsigned int) ep->dma_buf, ®->out_endp[ep_num].doepdma); writel(DOEPT_SIZ_PKT_CNT(pktcnt) | DOEPT_SIZ_XFER_SIZE(length), ®->out_endp[ep_num].doeptsiz);