@@ -454,6 +454,7 @@
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru HCLK_OTG0>;
clock-names = "otg";
+ dr_mode = "otg";
phys = <&usbphy0>;
phy-names = "usb2-phy";
status = "disabled";
@@ -52,6 +52,59 @@ void lowlevel_init(void)
{
}
+#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG)
+#include <usb.h>
+#include <usb/dwc2_udc.h>
+
+static struct dwc2_plat_otg_data rk3288_otg_data;
+
+int board_usb_init(int index, enum usb_init_type init)
+{
+ int offset;
+ const char *mode;
+ bool matched = false;
+ void *blob = gd->fdt_blob;
+ u32 base;
+
+ /* find the usb_otg node */
+ offset = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3288-usb");
+
+ while (offset != -FDT_ERR_NOTFOUND) {
+ mode = fdt_getprop(blob, offset, "dr_mode", NULL);
+ if (mode && strcmp(mode, "otg") == 0) {
+ matched = true;
+ break;
+ }
+
+ offset = fdt_node_offset_by_compatible(blob, offset,
+ "rockchip,rk3288-usb");
+ }
+ if (!matched) {
+ debug("Not found usb_otg device\n");
+ return -ENODEV;
+ }
+ rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, offset, "reg");
+
+ /* find the grf node */
+ offset = fdt_node_offset_by_compatible(blob, -1,
+ "rockchip,rk3288-grf");
+
+ if (offset == -FDT_ERR_NOTFOUND) {
+ debug("Not found grf device\n");
+ return -ENODEV;
+ }
+ rk3288_otg_data.regs_phy = fdtdec_get_addr(blob, offset, "reg");
+
+ return dwc2_udc_probe(&rk3288_otg_data);
+}
+
+int board_usb_cleanup(int index, enum usb_init_type init)
+{
+ return 0;
+}
+#endif
+
static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
@@ -80,6 +80,32 @@
#define CONFIG_SPI
#define CONFIG_SF_DEFAULT_SPEED 20000000
+/* usb otg */
+#define CONFIG_USB_GADGET
+#define CONFIG_USB_GADGET_DUALSPEED
+#define CONFIG_USB_GADGET_DWC2_OTG
+#define CONFIG_ROCKCHIP_USB_SYNO_PHY
+#define CONFIG_USB_GADGET_VBUS_DRAW 0
+
+/* fastboot */
+#define CONFIG_CMD_FASTBOOT
+#define CONFIG_USB_FUNCTION_FASTBOOT
+#define CONFIG_FASTBOOT_FLASH
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */
+/* stroe safely fastboot buffer data to the middle of bank */
+#define CONFIG_FASTBOOT_BUF_ADDR (CONFIG_SYS_SDRAM_BASE \
+ + SDRAM_BANK_SIZE / 2)
+#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000
+
+#define CONFIG_USB_GADGET_DOWNLOAD
+#define CONFIG_G_DNL_MANUFACTURER "Rockchip"
+#define CONFIG_G_DNL_VENDOR_NUM 0x2207
+#define CONFIG_G_DNL_PRODUCT_NUM 0x320a
+
+/* Enable gpt partition table */
+#define CONFIG_CMD_GPT
+#define CONFIG_EFI_PARTITION
+
#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>