diff mbox

[16/17,ARM] Add tests for VFP FP16 ACLE instrinsics.

Message ID 577A7034.1090709@foss.arm.com
State New
Headers show

Commit Message

Matthew Wahab July 4, 2016, 2:18 p.m. UTC 
On 18/05/16 11:58, Matthew Wahab wrote:
 > On 18/05/16 02:06, Joseph Myers wrote:
 >> On Tue, 17 May 2016, Matthew Wahab wrote:
 >>
 >>> In some tests, there are unavoidable differences in precision when
 >>> calculating the actual and the expected results of an FP16 operation. A
 >>> new support function CHECK_FP_BIAS is used so that these tests can check
 >>> for an acceptable margin of error. In these tests, the tolerance is
 >>> given as the absolute integer difference between the bitvectors of the
 >>> expected and the actual results.
 >>
 >> As far as I can see, CHECK_FP_BIAS is only used in the following patch,
 >> but there is another bias test in vsqrth_f16_1.c in this patch.
 >
 > This is my mistake, the CHECK_FP_BIAS is used for the NEON tests and should
 >  have gone into that patch. The VFP test can do a simpler check so doesn't
 > need the macro.
 >
 >> Could you clarify where the "unavoidable differences in precision" come
 >> from? Are the results of some of the new instructions not fully specified,
 >> only specified within a given precision?  (As far as I can tell the
 >> existing v8 instructions for reciprocal and reciprocal square root
 >> estimates do have fully defined results, despite being loosely described
 >> as esimtates.)
 >
 > The expected results in the new tests are represented as expressions whose
 > value is expected to be calculated at compile-time. This makes the tests
 > more readable but differences in the precision between the the compiler and
 > the HW calculations mean that for vrecpe_f16, vrecps_f16, vrsqrts_f16 and
 > vsqrth_f16_1.c the expected and actual results are different.
 >
 > On reflection, it may be better to remove the CHECK_FP_BIAS macro and, for
 > the tests that needed it, to drop the compiler calculation and just use the
 >  expected hexadecimal value.
 >
 > Other tests depending on compiler-time calculations involve relatively
 > simple arithmetic operations and it's not clear if they are susceptible to
 > the same rounding errors. I have limited knowledge in FP arithmetic though
 > so I'll look into this.

The scalar tests added in this patch and the vector tests added in the
next patch have been reworked to use the exact values for the expected
results rather than compile-time expressions. The CHECK_FP_BIAS macro is
not used and is removed from this patch.

The intention with these tests and with the vector tests is to check
that the compiler emits code that produces the same results as the
instruction regardless of any optimizations that it may apply. The
expected results for the tests were produced using inline assembler
taking the same inputs as the intrinsics being tested.

Other changes are to add and use some (limited) templates for scalar
operations and to add progress and error reporting, making the scalar
tests more consistent with those for the vector operations.

Tested the series for arm-none-linux-gnueabihf with native bootstrap and
make check and for arm-none-eabi and armeb-none-eabi with make check on
an ARMv8.2-A emulator.

Ok for trunk?
Matthew

testsuite/
2016-07-04  Jiong Wang  <jiong.wang@arm.com>
	    Matthew Wahab  <matthew.wahab@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc: New.
	* gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc: New.
	* gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc: New.
	* gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c: New.

Comments

Ramana Radhakrishnan Aug. 4, 2016, 8:35 a.m. UTC | #1 
On Mon, Jul 4, 2016 at 3:18 PM, Matthew Wahab
<matthew.wahab@foss.arm.com> wrote:
> On 18/05/16 11:58, Matthew Wahab wrote:
>> On 18/05/16 02:06, Joseph Myers wrote:
>>> On Tue, 17 May 2016, Matthew Wahab wrote:
>>>
>>>> In some tests, there are unavoidable differences in precision when
>>>> calculating the actual and the expected results of an FP16 operation. A
>>>> new support function CHECK_FP_BIAS is used so that these tests can check
>>>> for an acceptable margin of error. In these tests, the tolerance is
>>>> given as the absolute integer difference between the bitvectors of the
>>>> expected and the actual results.
>>>
>>> As far as I can see, CHECK_FP_BIAS is only used in the following patch,
>>> but there is another bias test in vsqrth_f16_1.c in this patch.
>>
>> This is my mistake, the CHECK_FP_BIAS is used for the NEON tests and
>> should
>>  have gone into that patch. The VFP test can do a simpler check so doesn't
>> need the macro.
>>
>>> Could you clarify where the "unavoidable differences in precision" come
>>> from? Are the results of some of the new instructions not fully
>>> specified,
>>> only specified within a given precision?  (As far as I can tell the
>>> existing v8 instructions for reciprocal and reciprocal square root
>>> estimates do have fully defined results, despite being loosely described
>>> as esimtates.)
>>
>> The expected results in the new tests are represented as expressions whose
>> value is expected to be calculated at compile-time. This makes the tests
>> more readable but differences in the precision between the the compiler
>> and
>> the HW calculations mean that for vrecpe_f16, vrecps_f16, vrsqrts_f16 and
>> vsqrth_f16_1.c the expected and actual results are different.
>>
>> On reflection, it may be better to remove the CHECK_FP_BIAS macro and, for
>> the tests that needed it, to drop the compiler calculation and just use
>> the
>>  expected hexadecimal value.
>>
>> Other tests depending on compiler-time calculations involve relatively
>> simple arithmetic operations and it's not clear if they are susceptible to
>> the same rounding errors. I have limited knowledge in FP arithmetic though
>> so I'll look into this.
>
> The scalar tests added in this patch and the vector tests added in the
> next patch have been reworked to use the exact values for the expected
> results rather than compile-time expressions. The CHECK_FP_BIAS macro is
> not used and is removed from this patch.
>
> The intention with these tests and with the vector tests is to check
> that the compiler emits code that produces the same results as the
> instruction regardless of any optimizations that it may apply. The
> expected results for the tests were produced using inline assembler
> taking the same inputs as the intrinsics being tested.
>
> Other changes are to add and use some (limited) templates for scalar
> operations and to add progress and error reporting, making the scalar
> tests more consistent with those for the vector operations.
>
> Tested the series for arm-none-linux-gnueabihf with native bootstrap and
> make check and for arm-none-eabi and armeb-none-eabi with make check on
> an ARMv8.2-A emulator.
>
> Ok for trunk?
> Matthew
>

OK, please watch out for any fallout from the autotesters especially
with strange multilib combinations.

Ramana

> testsuite/
> 2016-07-04  Jiong Wang  <jiong.wang@arm.com>
>             Matthew Wahab  <matthew.wahab@arm.com>
>
>         * gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc: New.
>         * gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc: New.
>         * gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc: New.
>
>         * gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c: New.
>         * gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c: New.
>
diff mbox

Patch

From a2ad09ded8e34f4e42b7bba1c04c8b2d0f5c9fdd Mon Sep 17 00:00:00 2001
From: Matthew Wahab <matthew.wahab@arm.com>
Date: Thu, 7 Apr 2016 15:40:52 +0100
Subject: [PATCH 16/17] [PATCH 16/17][ARM] Add tests for VFP FP16 ACLE
 instrinsics.

testsuite/
2016-07-04  Jiong Wang  <jiong.wang@arm.com>
	    Matthew Wahab  <matthew.wahab@arm.com>

	* gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc: New.
	* gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc: New.
	* gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc: New.
	* gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c: New.
	* gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c: New.
---
 .../advsimd-intrinsics/binary_scalar_op.inc        | 160 ++++++++++++++++
 .../advsimd-intrinsics/ternary_scalar_op.inc       | 206 +++++++++++++++++++++
 .../aarch64/advsimd-intrinsics/unary_scalar_op.inc | 199 ++++++++++++++++++++
 .../aarch64/advsimd-intrinsics/vabsh_f16_1.c       |  40 ++++
 .../aarch64/advsimd-intrinsics/vaddh_f16_1.c       |  40 ++++
 .../aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c  |  53 ++++++
 .../aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c  |  53 ++++++
 .../aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c   |  52 ++++++
 .../aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c   |  52 ++++++
 .../aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c |  99 ++++++++++
 .../aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c |  99 ++++++++++
 .../aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c | 100 ++++++++++
 .../aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c | 100 ++++++++++
 .../aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c   |  53 ++++++
 .../aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c   |  53 ++++++
 .../aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c  |  53 ++++++
 .../aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c  |  53 ++++++
 .../aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c  |  53 ++++++
 .../aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c  |  53 ++++++
 .../aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c  |  53 ++++++
 .../aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c  |  53 ++++++
 .../aarch64/advsimd-intrinsics/vdivh_f16_1.c       |  42 +++++
 .../aarch64/advsimd-intrinsics/vfmah_f16_1.c       |  40 ++++
 .../aarch64/advsimd-intrinsics/vfmsh_f16_1.c       |  40 ++++
 .../aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c     |  42 +++++
 .../aarch64/advsimd-intrinsics/vminnmh_f16_1.c     |  42 +++++
 .../aarch64/advsimd-intrinsics/vmulh_f16_1.c       |  42 +++++
 .../aarch64/advsimd-intrinsics/vnegh_f16_1.c       |  39 ++++
 .../aarch64/advsimd-intrinsics/vrndah_f16_1.c      |  40 ++++
 .../aarch64/advsimd-intrinsics/vrndh_f16_1.c       |  40 ++++
 .../aarch64/advsimd-intrinsics/vrndih_f16_1.c      |  40 ++++
 .../aarch64/advsimd-intrinsics/vrndmh_f16_1.c      |  40 ++++
 .../aarch64/advsimd-intrinsics/vrndnh_f16_1.c      |  40 ++++
 .../aarch64/advsimd-intrinsics/vrndph_f16_1.c      |  40 ++++
 .../aarch64/advsimd-intrinsics/vrndxh_f16_1.c      |  40 ++++
 .../aarch64/advsimd-intrinsics/vsqrth_f16_1.c      |  40 ++++
 .../aarch64/advsimd-intrinsics/vsubh_f16_1.c       |  42 +++++
 37 files changed, 2326 insertions(+)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c
 create mode 100644 gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c

diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc
new file mode 100644
index 0000000..55dedd4
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/binary_scalar_op.inc
@@ -0,0 +1,160 @@ 
+/* Template file for binary scalar operator validation.
+
+   This file is meant to be included by test files for binary scalar
+   operations.  */
+
+/* Check for required settings.  */
+
+#ifndef INSN_NAME
+#error INSN_NAME (the intrinsic to test) must be defined.
+#endif
+
+#ifndef INPUT_TYPE
+#error INPUT_TYPE (basic type of an input value) must be defined.
+#endif
+
+#ifndef OUTPUT_TYPE
+#error OUTPUT_TYPE (basic type of an output value) must be defined.
+#endif
+
+#ifndef OUTPUT_TYPE_SIZE
+#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined.
+#endif
+
+/* Optional settings:
+
+   INPUT_1: Input values for the first parameter.  Must be of type INPUT_TYPE.
+   INPUT_2: Input values for the first parameter.  Must be of type
+   INPUT_TYPE.  */
+
+#ifndef TEST_MSG
+#define TEST_MSG "unnamed test"
+#endif
+
+/* The test framework.  */
+
+#include <stdio.h>
+
+extern void abort ();
+
+#define INFF __builtin_inf ()
+
+/* Stringify a macro.  */
+#define STR0(A) #A
+#define STR(A) STR0 (A)
+
+/* Macro concatenation.  */
+#define CAT0(A, B) A##B
+#define CAT(A, B) CAT0 (A, B)
+
+/* Format strings for error reporting.  */
+#define FMT16 "0x%04x"
+#define FMT32 "0x%08x"
+#define FMT CAT (FMT,OUTPUT_TYPE_SIZE)
+
+/* Type construction: forms TS_t, where T is the base type and S the size in
+   bits.  */
+#define MK_TYPE0(T, S) T##S##_t
+#define MK_TYPE(T, S) MK_TYPE0 (T, S)
+
+/* Convenience types for input and output data.  */
+typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type;
+
+/* Conversion between typed values and their hexadecimal representation.  */
+typedef union
+{
+  OUTPUT_TYPE value;
+  output_hex_type hex;
+} output_conv_type;
+
+/* Default input values.  */
+
+float16_t input_1_float16_t[] =
+{
+  0.0, -0.0,
+  2.0, 3.1,
+  20.0, 0.40,
+  -2.3, 1.33,
+  -7.6, 0.31,
+  0.3353, 0.5,
+  1.0, 13.13,
+  -6.3, 20.0,
+  (float16_t)INFF, (float16_t)-INFF,
+};
+
+float16_t input_2_float16_t[] =
+{
+  1.0, 1.0,
+  -4.33, 100.0,
+  30.0, -0.02,
+  0.5, -7.231,
+  -6.3, 20.0,
+  -7.231, 2.3,
+  -7.6, 5.1,
+  0.31, 0.33353,
+  (float16_t)-INFF, (float16_t)INFF,
+};
+
+#ifndef INPUT_1
+#define INPUT_1 CAT (input_1_,INPUT_TYPE)
+#endif
+
+#ifndef INPUT_2
+#define INPUT_2 CAT (input_2_,INPUT_TYPE)
+#endif
+
+/* Support macros and routines for the test function.  */
+
+#define CHECK()						\
+  {								\
+    output_conv_type actual;					\
+    output_conv_type expect;					\
+								\
+    expect.hex = ((output_hex_type*)EXPECTED)[index];		\
+    actual.value = INSN_NAME ((INPUT_1)[index],			\
+			      (INPUT_2)[index]);		\
+								\
+    if (actual.hex != expect.hex)				\
+      {								\
+	fprintf (stderr,					\
+		 "ERROR in %s (%s line %d), buffer %s, "	\
+		 "index %d: got "				\
+		 FMT " != " FMT "\n",				\
+		 TEST_MSG, __FILE__, __LINE__,			\
+		 STR (EXPECTED), index,				\
+		 actual.hex, expect.hex);			\
+	abort ();						\
+      }								\
+    fprintf (stderr, "CHECKED %s %s\n",				\
+	     STR (EXPECTED), TEST_MSG);				\
+  }
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1 (NAME)
+
+/* The test function.  */
+
+void
+FNNAME (INSN_NAME) (void)
+{
+  /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result
+     against EXPECTED[i].  */
+
+  const int num_tests = sizeof (INPUT_1) / sizeof (INPUT_1[0]);
+  int index;
+
+  for (index = 0; index < num_tests; index++)
+    CHECK ();
+
+#ifdef EXTRA_TESTS
+  EXTRA_TESTS ();
+#endif
+}
+
+int
+main (void)
+{
+  FNNAME (INSN_NAME) ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc
new file mode 100644
index 0000000..4765091
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/ternary_scalar_op.inc
@@ -0,0 +1,206 @@ 
+/* Template file for ternary scalar operator validation.
+
+   This file is meant to be included by test files for binary scalar
+   operations.  */
+
+/* Check for required settings.  */
+
+#ifndef INSN_NAME
+#error INSN_NAME (the intrinsic to test) must be defined.
+#endif
+
+#ifndef INPUT_TYPE
+#error INPUT_TYPE (basic type of an input value) must be defined.
+#endif
+
+#ifndef OUTPUT_TYPE
+#error OUTPUT_TYPE (basic type of an output value) must be defined.
+#endif
+
+#ifndef OUTPUT_TYPE_SIZE
+#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined.
+#endif
+
+/* Optional settings:
+
+   INPUT_1: Input values for the first parameter.  Must be of type INPUT_TYPE.
+   INPUT_2: Input values for the second parameter.  Must be of type INPUT_TYPE.
+   INPUT_3: Input values for the third parameter.  Must be of type
+   INPUT_TYPE.  */
+
+#ifndef TEST_MSG
+#define TEST_MSG "unnamed test"
+#endif
+
+/* The test framework.  */
+
+#include <stdio.h>
+
+extern void abort ();
+
+#define INFF __builtin_inf ()
+
+/* Stringify a macro.  */
+#define STR0(A) #A
+#define STR(A) STR0 (A)
+
+/* Macro concatenation.  */
+#define CAT0(A, B) A##B
+#define CAT(A, B) CAT0 (A, B)
+
+/* Format strings for error reporting.  */
+#define FMT16 "0x%04x"
+#define FMT32 "0x%08x"
+#define FMT CAT (FMT,OUTPUT_TYPE_SIZE)
+
+/* Type construction: forms TS_t, where T is the base type and S the size in
+   bits.  */
+#define MK_TYPE0(T, S) T##S##_t
+#define MK_TYPE(T, S) MK_TYPE0 (T, S)
+
+/* Convenience types for input and output data.  */
+typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type;
+
+/* Conversion between typed values and their hexadecimal representation.  */
+typedef union
+{
+  OUTPUT_TYPE value;
+  output_hex_type hex;
+} output_conv_type;
+
+/* Default input values.  */
+
+float16_t input_1_float16_t[] =
+{
+  0.0,
+  -0.0,
+  2.0,
+  3.1,
+  20.0,
+  0.40,
+  -2.3,
+  1.33,
+  -7.6,
+  0.31,
+  0.3353,
+  0.5,
+  1.0,
+  13.13,
+  -6.3,
+  20.0,
+  (float16_t)INFF,
+  (float16_t)-INFF,
+};
+
+float16_t input_2_float16_t[] =
+{
+  1.0,
+  1.0,
+  -4.33,
+  100.0,
+  30.0,
+  -0.02,
+  0.5,
+  -7.231,
+  -6.3,
+  20.0,
+  -7.231,
+  2.3,
+  -7.6,
+  5.1,
+  0.31,
+  0.33353,
+  (float16_t)-INFF,
+  (float16_t)INFF,
+};
+
+float16_t input_3_float16_t[] =
+{
+  -0.0,
+  0.0,
+  0.31,
+  -0.31,
+  1.31,
+  2.1,
+  -6.3,
+  1.0,
+  -1.5,
+  5.1,
+  0.3353,
+  9.3,
+  -9.3,
+  -7.231,
+  0.5,
+  -0.33,
+  (float16_t)INFF,
+  (float16_t)INFF,
+};
+
+#ifndef INPUT_1
+#define INPUT_1 CAT (input_1_,INPUT_TYPE)
+#endif
+
+#ifndef INPUT_2
+#define INPUT_2 CAT (input_2_,INPUT_TYPE)
+#endif
+
+#ifndef INPUT_3
+#define INPUT_3 CAT (input_3_,INPUT_TYPE)
+#endif
+
+/* Support macros and routines for the test function.  */
+
+#define CHECK()							\
+  {								\
+    output_conv_type actual;					\
+    output_conv_type expect;					\
+								\
+    expect.hex = ((output_hex_type*)EXPECTED)[index];		\
+    actual.value = INSN_NAME ((INPUT_1)[index],			\
+			      (INPUT_2)[index],			\
+			      (INPUT_3)[index]);		\
+								\
+    if (actual.hex != expect.hex)				\
+      {								\
+	fprintf (stderr,					\
+		 "ERROR in %s (%s line %d), buffer %s, "	\
+		 "index %d: got "				\
+		 FMT " != " FMT "\n",				\
+		 TEST_MSG, __FILE__, __LINE__,			\
+		 STR (EXPECTED), index,				\
+		 actual.hex, expect.hex);			\
+	abort ();						\
+      }								\
+    fprintf (stderr, "CHECKED %s %s\n",				\
+	     STR (EXPECTED), TEST_MSG);				\
+  }
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1 (NAME)
+
+/* The test function.  */
+
+void
+FNNAME (INSN_NAME) (void)
+{
+  /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result
+     against EXPECTED[i].  */
+
+  const int num_tests = sizeof (INPUT_1) / sizeof (INPUT_1[0]);
+  int index;
+
+  for (index = 0; index < num_tests; index++)
+    CHECK ();
+
+#ifdef EXTRA_TESTS
+  EXTRA_TESTS ();
+#endif
+}
+
+int
+main (void)
+{
+  FNNAME (INSN_NAME) ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc
new file mode 100644
index 0000000..86403d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/unary_scalar_op.inc
@@ -0,0 +1,199 @@ 
+/* Template file for unary scalar operator validation.
+
+   This file is meant to be included by test files for unary scalar
+   operations.  */
+
+/* Check for required settings.  */
+
+#ifndef INSN_NAME
+#error INSN_NAME (the intrinsic to test) must be defined.
+#endif
+
+#ifndef INPUT_TYPE
+#error INPUT_TYPE (basic type of an input value) must be defined.
+#endif
+
+#ifndef SCALAR_OPERANDS
+#ifndef EXPECTED
+#error EXPECTED (an array of expected output values) must be defined.
+#endif
+#endif
+
+#ifndef OUTPUT_TYPE
+#error OUTPUT_TYPE (basic type of an output value) must be defined.
+#endif
+
+#ifndef OUTPUT_TYPE_SIZE
+#error OUTPUT_TYPE_SIZE (size in bits of an output value) must be defined.
+#endif
+
+/* Optional settings.  */
+
+/* SCALAR_OPERANDS: Defined iff the intrinsic has a scalar operand.
+
+   SCALAR_1, SCALAR_2, .., SCALAR_4: If SCALAR_OPERANDS is defined, SCALAR_<n>
+   is the scalar and EXPECTED_<n> is array of expected values.
+
+   INPUT: Input values for the first parameter.  Must be of type INPUT_TYPE.  */
+
+/* Additional comments for the error message.  */
+#ifndef COMMENT
+#define COMMENT ""
+#endif
+
+#ifndef TEST_MSG
+#define TEST_MSG "unnamed test"
+#endif
+
+/* The test framework.  */
+
+#include <stdio.h>
+
+extern void abort ();
+
+#define INFF __builtin_inf ()
+
+/* Stringify a macro.  */
+#define STR0(A) #A
+#define STR(A) STR0 (A)
+
+/* Macro concatenation.  */
+#define CAT0(A, B) A##B
+#define CAT(A, B) CAT0 (A, B)
+
+/* Format strings for error reporting.  */
+#define FMT16 "0x%04x"
+#define FMT32 "0x%08x"
+#define FMT CAT (FMT,OUTPUT_TYPE_SIZE)
+
+/* Type construction: forms TS_t, where T is the base type and S the size in
+   bits.  */
+#define MK_TYPE0(T, S) T##S##_t
+#define MK_TYPE(T, S) MK_TYPE0 (T, S)
+
+/* Convenience types for input and output data.  */
+typedef MK_TYPE (uint, OUTPUT_TYPE_SIZE) output_hex_type;
+
+/* Conversion between typed values and their hexadecimal representation.  */
+typedef union
+{
+  OUTPUT_TYPE value;
+  output_hex_type hex;
+} output_conv_type;
+
+/* Default input values.  */
+
+float16_t input_1_float16_t[] =
+{
+  0.0, -0.0,
+  2.0, 3.1,
+  20.0, 0.40,
+  -2.3, 1.33,
+  -7.6, 0.31,
+  0.3353, 0.5,
+  1.0, 13.13,
+  -6.3, 20.0,
+  (float16_t)INFF, (float16_t)-INFF,
+};
+
+#ifndef INPUT
+#define INPUT CAT(input_1_,INPUT_TYPE)
+#endif
+
+/* Support macros and routines for the test function.  */
+
+#define CHECK()							\
+  {								\
+    output_conv_type actual;					\
+    output_conv_type expect;					\
+								\
+    expect.hex = ((output_hex_type*)EXPECTED)[index];		\
+    actual.value = INSN_NAME ((INPUT)[index]);			\
+								\
+    if (actual.hex != expect.hex)				\
+      {								\
+	fprintf (stderr,					\
+		 "ERROR in %s (%s line %d), buffer %s, "	\
+		 "index %d: got "				\
+		 FMT " != " FMT "\n",				\
+		 TEST_MSG, __FILE__, __LINE__,			\
+		 STR (EXPECTED), index,				\
+		 actual.hex, expect.hex);			\
+	abort ();						\
+      }								\
+    fprintf (stderr, "CHECKED %s %s\n",				\
+	     STR (EXPECTED), TEST_MSG);				\
+  }
+
+#define CHECK_N(SCALAR, EXPECTED)				\
+  {								\
+    output_conv_type actual;					\
+    output_conv_type expect;					\
+								\
+    expect.hex							\
+      = ((output_hex_type*)EXPECTED)[index];			\
+    actual.value = INSN_NAME ((INPUT)[index], (SCALAR));	\
+								\
+    if (actual.hex != expect.hex)				\
+      {								\
+	fprintf (stderr,					\
+		 "ERROR in %s (%s line %d), buffer %s, "	\
+		 "index %d: got "				\
+		 FMT " != " FMT "\n",				\
+		 TEST_MSG, __FILE__, __LINE__,			\
+		 STR (EXPECTED), index,				\
+		 actual.hex, expect.hex);			\
+	abort ();						\
+      }								\
+    fprintf (stderr, "CHECKED %s %s\n",				\
+	     STR (EXPECTED), TEST_MSG);				\
+  }
+
+#define FNNAME1(NAME) exec_ ## NAME
+#define FNNAME(NAME) FNNAME1 (NAME)
+
+/* The test function.  */
+
+void
+FNNAME (INSN_NAME) (void)
+{
+  /* Basic test: y[i] = OP (x[i]), for each INPUT[i], then compare the result
+     against EXPECTED[i].  */
+
+  const int num_tests = sizeof (INPUT) / sizeof (INPUT[0]);
+  int index;
+
+  for (index = 0; index < num_tests; index++)
+    {
+#if defined (SCALAR_OPERANDS)
+
+#ifdef SCALAR_1
+      CHECK_N (SCALAR_1, EXPECTED_1);
+#endif
+#ifdef SCALAR_2
+      CHECK_N (SCALAR_2, EXPECTED_2);
+#endif
+#ifdef SCALAR_3
+      CHECK_N (SCALAR_3, EXPECTED_3);
+#endif
+#ifdef SCALAR_4
+      CHECK_N (SCALAR_4, EXPECTED_4);
+#endif
+
+#else /* !defined (SCALAR_OPERAND).  */
+      CHECK ();
+#endif
+    }
+
+#ifdef EXTRA_TESTS
+  EXTRA_TESTS ();
+#endif
+}
+
+int
+main (void)
+{
+  FNNAME (INSN_NAME) ();
+
+  return 0;
+}
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c
new file mode 100644
index 0000000..16a986a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vabsh_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x4000 /* 2.000000 */,
+  0x4233 /* 3.099609 */,
+  0x4d00 /* 20.000000 */,
+  0x3666 /* 0.399902 */,
+  0x409a /* 2.300781 */,
+  0x3d52 /* 1.330078 */,
+  0x479a /* 7.601562 */,
+  0x34f6 /* 0.310059 */,
+  0x355d /* 0.335205 */,
+  0x3800 /* 0.500000 */,
+  0x3c00 /* 1.000000 */,
+  0x4a91 /* 13.132812 */,
+  0x464d /* 6.300781 */,
+  0x4d00 /* 20.000000 */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */
+};
+
+#define TEST_MSG "VABSH_F16"
+#define INSN_NAME vabsh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c
new file mode 100644
index 0000000..4b0e242
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vaddh_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0xc0a8 /* -2.328125 */,
+  0x5672 /* 103.125000 */,
+  0x5240 /* 50.000000 */,
+  0x3614 /* 0.379883 */,
+  0xbf34 /* -1.800781 */,
+  0xc5e6 /* -5.898438 */,
+  0xcaf4 /* -13.906250 */,
+  0x4d14 /* 20.312500 */,
+  0xc6e5 /* -6.894531 */,
+  0x419a /* 2.800781 */,
+  0xc69a /* -6.601562 */,
+  0x4c8f /* 18.234375 */,
+  0xc5fe /* -5.992188 */,
+  0x4d15 /* 20.328125 */,
+  0x7e00 /* nan */,
+  0x7e00 /* nan */,
+};
+
+#define TEST_MSG "VADDH_F16"
+#define INSN_NAME vaddh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for binary scalar operations.  */
+#include "binary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c
new file mode 100644
index 0000000..ebfd62a
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_s32_f16_1.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected[] =
+{
+  0x00000000,
+  0x00000000,
+  0x0000007b,
+  0xfffffdc8,
+  0xffffffdd,
+  0x00000400,
+  0x00000297,
+  0x000000a9,
+  0xfffffffb,
+  0x0000004d,
+  0xffffff6f,
+  0xffffffc7,
+  0xfffffff0,
+  0xfffffff1,
+  0xfffffff2,
+  0xfffffff3
+};
+
+#define TEST_MSG "VCVTAH_S32_F16"
+#define INSN_NAME vcvtah_s32_f16
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE int32_t
+#define OUTPUT_TYPE_SIZE 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c
new file mode 100644
index 0000000..5ae28fc
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtah_u32_f16_1.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected[] =
+{
+  0x00000000,
+  0x00000000,
+  0x0000007b,
+  0x00000000,
+  0x00000000,
+  0x00000400,
+  0x00000297,
+  0x000000a9,
+  0x00000000,
+  0x0000004d,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000
+};
+
+#define TEST_MSG "VCVTAH_U32_F16"
+#define INSN_NAME vcvtah_u32_f16
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE uint32_t
+#define OUTPUT_TYPE_SIZE 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c
new file mode 100644
index 0000000..2173a0e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_s32_1.c
@@ -0,0 +1,52 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+uint32_t input[] =
+{
+  0, -0,
+  123, -567,
+  -34, 1024,
+  -63, 169,
+  -4, 77,
+  -144, -56,
+  -16, -15,
+  -14, -13,
+};
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x57b0 /* 123.000000 */,
+  0xe06e /* -567.000000 */,
+  0xd040 /* -34.000000 */,
+  0x6400 /* 1024.000000 */,
+  0xd3e0 /* -63.000000 */,
+  0x5948 /* 169.000000 */,
+  0xc400 /* -4.000000 */,
+  0x54d0 /* 77.000000 */,
+  0xd880 /* -144.000000 */,
+  0xd300 /* -56.000000 */,
+  0xcc00 /* -16.000000 */,
+  0xcb80 /* -15.000000 */,
+  0xcb00 /* -14.000000 */,
+  0xca80 /* -13.000000 */
+};
+
+#define TEST_MSG "VCVTH_F16_S32"
+#define INSN_NAME vcvth_f16_s32
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE uint32_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c
new file mode 100644
index 0000000..1583202
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_f16_u32_1.c
@@ -0,0 +1,52 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+int32_t input[] =
+{
+  0, -0,
+  123, -567,
+  -34, 1024,
+  -63, 169,
+  -4, 77,
+  -144, -56,
+  -16, -15,
+  -14, -13,
+};
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x57b0 /* 123.000000 */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x6400 /* 1024.000000 */,
+  0x7c00 /* inf */,
+  0x5948 /* 169.000000 */,
+  0x7c00 /* inf */,
+  0x54d0 /* 77.000000 */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */
+};
+
+#define TEST_MSG "VCVTH_F16_U32"
+#define INSN_NAME vcvth_f16_u32
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE int32_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c
new file mode 100644
index 0000000..9ce9558
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_s32_1.c
@@ -0,0 +1,99 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+uint32_t input[] =
+{
+  0, -0,
+  123, -567,
+  -34, 1024,
+  -63, 169,
+  -4, 77,
+  -144, -56,
+  -16, -15,
+  -14, -13,
+};
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected_1[] =
+{
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x53b0 /* 61.500000 */,
+  0xdc6e /* -283.500000 */,
+  0xcc40 /* -17.000000 */,
+  0x6000 /* 512.000000 */,
+  0xcfe0 /* -31.500000 */,
+  0x5548 /* 84.500000 */,
+  0xc000 /* -2.000000 */,
+  0x50d0 /* 38.500000 */,
+  0xd480 /* -72.000000 */,
+  0xcf00 /* -28.000000 */,
+  0xc800 /* -8.000000 */,
+  0xc780 /* -7.500000 */,
+  0xc700 /* -7.000000 */,
+  0xc680 /* -6.500000 */
+};
+
+uint16_t expected_2[] =
+{
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x4fb0 /* 30.750000 */,
+  0xd86e /* -141.750000 */,
+  0xc840 /* -8.500000 */,
+  0x5c00 /* 256.000000 */,
+  0xcbe0 /* -15.750000 */,
+  0x5148 /* 42.250000 */,
+  0xbc00 /* -1.000000 */,
+  0x4cd0 /* 19.250000 */,
+  0xd080 /* -36.000000 */,
+  0xcb00 /* -14.000000 */,
+  0xc400 /* -4.000000 */,
+  0xc380 /* -3.750000 */,
+  0xc300 /* -3.500000 */,
+  0xc280 /* -3.250000 */
+};
+
+uint16_t expected_3[] =
+{
+ 0x0000 /* 0.000000 */,
+ 0x0000 /* 0.000000 */,
+ 0x0000 /* 0.000000 */,
+ 0x8002 /* -0.000000 */,
+ 0x8000 /* -0.000000 */,
+ 0x0004 /* 0.000000 */,
+ 0x8000 /* -0.000000 */,
+ 0x0001 /* 0.000000 */,
+ 0x8000 /* -0.000000 */,
+ 0x0000 /* 0.000000 */,
+ 0x8001 /* -0.000000 */,
+ 0x8000 /* -0.000000 */,
+ 0x8000 /* -0.000000 */,
+ 0x8000 /* -0.000000 */,
+ 0x8000 /* -0.000000 */,
+ 0x8000 /* -0.000000 */
+};
+
+#define TEST_MSG "VCVTH_N_F16_S32"
+#define INSN_NAME vcvth_n_f16_s32
+
+#define INPUT input
+#define EXPECTED_1 expected_1
+#define EXPECTED_2 expected_2
+#define EXPECTED_3 expected_3
+
+#define INPUT_TYPE int32_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+#define SCALAR_OPERANDS
+#define SCALAR_1 1
+#define SCALAR_2 2
+#define SCALAR_3 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c
new file mode 100644
index 0000000..d308c35
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_f16_u32_1.c
@@ -0,0 +1,99 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+uint32_t input[] =
+{
+  0, -0,
+  123, -567,
+  -34, 1024,
+  -63, 169,
+  -4, 77,
+  -144, -56,
+  -16, -15,
+  -14, -13,
+};
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected_1[] =
+{
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x53b0 /* 61.500000 */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x6000 /* 512.000000 */,
+  0x7c00 /* inf */,
+  0x5548 /* 84.500000 */,
+  0x7c00 /* inf */,
+  0x50d0 /* 38.500000 */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */
+};
+
+uint16_t expected_2[] =
+{
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x4fb0 /* 30.750000 */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x5c00 /* 256.000000 */,
+  0x7c00 /* inf */,
+  0x5148 /* 42.250000 */,
+  0x7c00 /* inf */,
+  0x4cd0 /* 19.250000 */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */
+};
+
+uint16_t expected_3[] =
+{
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x0004 /* 0.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x0001 /* 0.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x0000 /* 0.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */
+};
+
+#define TEST_MSG "VCVTH_N_F16_U32"
+#define INSN_NAME vcvth_n_f16_u32
+
+#define INPUT input
+#define EXPECTED_1 expected_1
+#define EXPECTED_2 expected_2
+#define EXPECTED_3 expected_3
+
+#define INPUT_TYPE uint32_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+#define SCALAR_OPERANDS
+#define SCALAR_1 1
+#define SCALAR_2 2
+#define SCALAR_3 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c
new file mode 100644
index 0000000..6e2ee50
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_s32_f16_1.c
@@ -0,0 +1,100 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected_1[] =
+{
+  0x00000000,
+  0x00000000,
+  0x000000f6,
+  0xfffffb90,
+  0xffffffbb,
+  0x00000800,
+  0x0000052e,
+  0x00000152,
+  0xfffffff7,
+  0x0000009a,
+  0xfffffedf,
+  0xffffff8f,
+  0xffffffe0,
+  0xffffffe2,
+  0xffffffe4,
+  0xffffffe6,
+};
+
+uint32_t expected_2[] =
+{
+  0x00000000,
+  0x00000000,
+  0x000001ed,
+  0xfffff720,
+  0xffffff75,
+  0x00001000,
+  0x00000a5c,
+  0x000002a4,
+  0xffffffed,
+  0x00000134,
+  0xfffffdbe,
+  0xffffff1d,
+  0xffffffc0,
+  0xffffffc4,
+  0xffffffc8,
+  0xffffffcc,
+};
+
+uint32_t expected_3[] =
+{
+  0x00000000,
+  0x00000000,
+  0x7fffffff,
+  0x80000000,
+  0x80000000,
+  0x7fffffff,
+  0x7fffffff,
+  0x7fffffff,
+  0x80000000,
+  0x7fffffff,
+  0x80000000,
+  0x80000000,
+  0x80000000,
+  0x80000000,
+  0x80000000,
+  0x80000000,
+};
+
+#define TEST_MSG "VCVTH_N_S32_F16"
+#define INSN_NAME vcvth_n_s32_f16
+
+#define INPUT input
+#define EXPECTED_1 expected_1
+#define EXPECTED_2 expected_2
+#define EXPECTED_3 expected_3
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE uint32_t
+#define OUTPUT_TYPE_SIZE 32
+
+#define SCALAR_OPERANDS
+#define SCALAR_1 1
+#define SCALAR_2 2
+#define SCALAR_3 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c
new file mode 100644
index 0000000..188f60c
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_n_u32_f16_1.c
@@ -0,0 +1,100 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected_1[] =
+{
+  0x00000000,
+  0x00000000,
+  0x000000f6,
+  0x00000000,
+  0x00000000,
+  0x00000800,
+  0x0000052e,
+  0x00000152,
+  0x00000000,
+  0x0000009a,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+};
+
+uint32_t expected_2[] =
+{
+  0x00000000,
+  0x00000000,
+  0x000001ed,
+  0x00000000,
+  0x00000000,
+  0x00001000,
+  0x00000a5c,
+  0x000002a4,
+  0x00000000,
+  0x00000134,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+};
+
+uint32_t expected_3[] =
+{
+  0x00000000,
+  0x00000000,
+  0xffffffff,
+  0x00000000,
+  0x00000000,
+  0xffffffff,
+  0xffffffff,
+  0xffffffff,
+  0x00000000,
+  0xffffffff,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+};
+
+#define TEST_MSG "VCVTH_N_U32_F16"
+#define INSN_NAME vcvth_n_u32_f16
+
+#define INPUT input
+#define EXPECTED_1 expected_1
+#define EXPECTED_2 expected_2
+#define EXPECTED_3 expected_3
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE uint32_t
+#define OUTPUT_TYPE_SIZE 32
+
+#define SCALAR_OPERANDS
+#define SCALAR_1 1
+#define SCALAR_2 2
+#define SCALAR_3 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c
new file mode 100644
index 0000000..6bff954
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_s32_f16_1.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected[] =
+{
+  0x00000000,
+  0x00000000,
+  0x0000007b,
+  0xfffffdc8,
+  0xffffffde,
+  0x00000400,
+  0x00000297,
+  0x000000a9,
+  0xfffffffc,
+  0x0000004d,
+  0xffffff70,
+  0xffffffc8,
+  0xfffffff0,
+  0xfffffff1,
+  0xfffffff2,
+  0xfffffff3,
+};
+
+#define TEST_MSG "VCVTH_S32_F16"
+#define INSN_NAME vcvth_s32_f16
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE int32_t
+#define OUTPUT_TYPE_SIZE 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c
new file mode 100644
index 0000000..d5807d7
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvth_u32_f16_1.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected[] =
+{
+  0x00000000,
+  0x00000000,
+  0x0000007b,
+  0x00000000,
+  0x00000000,
+  0x00000400,
+  0x00000297,
+  0x000000a9,
+  0x00000000,
+  0x0000004d,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+};
+
+#define TEST_MSG "VCVTH_U32_F16"
+#define INSN_NAME vcvth_u32_f16
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE uint32_t
+#define OUTPUT_TYPE_SIZE 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c
new file mode 100644
index 0000000..f4f7b37
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_s32_f16_1.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected[] =
+{
+  0x00000000,
+  0x00000000,
+  0x0000007b,
+  0xfffffdc8,
+  0xffffffdd,
+  0x00000400,
+  0x00000297,
+  0x000000a9,
+  0xfffffffb,
+  0x0000004d,
+  0xffffff6f,
+  0xffffffc7,
+  0xfffffff0,
+  0xfffffff1,
+  0xfffffff2,
+  0xfffffff3
+};
+
+#define TEST_MSG "VCVTMH_S32_F16"
+#define INSN_NAME vcvtmh_s32_f16
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE int32_t
+#define OUTPUT_TYPE_SIZE 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c
new file mode 100644
index 0000000..6cda3b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtmh_u32_f16_1.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected[] =
+{
+  0x00000000,
+  0x00000000,
+  0x0000007b,
+  0x00000000,
+  0x00000000,
+  0x00000400,
+  0x00000297,
+  0x000000a9,
+  0x00000000,
+  0x0000004d,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+};
+
+#define TEST_MSG "VCVTMH_U32_F16"
+#define INSN_NAME vcvtmh_u32_f16
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE uint32_t
+#define OUTPUT_TYPE_SIZE 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c
new file mode 100644
index 0000000..94c333e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_s32_f16_1.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected[] =
+{
+  0x00000000,
+  0x00000000,
+  0x0000007b,
+  0xfffffdc8,
+  0xffffffdd,
+  0x00000400,
+  0x00000297,
+  0x000000a9,
+  0xfffffffb,
+  0x0000004d,
+  0xffffff70,
+  0xffffffc7,
+  0xfffffff0,
+  0xfffffff1,
+  0xfffffff2,
+  0xfffffff3
+};
+
+#define TEST_MSG "VCVTNH_S32_F16"
+#define INSN_NAME vcvtnh_s32_f16
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE int32_t
+#define OUTPUT_TYPE_SIZE 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c
new file mode 100644
index 0000000..97d5fba
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtnh_u32_f16_1.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected[] =
+{
+  0x00000000,
+  0x00000000,
+  0x0000007b,
+  0x00000000,
+  0x00000000,
+  0x00000400,
+  0x00000297,
+  0x000000a9,
+  0x00000000,
+  0x0000004d,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+};
+
+#define TEST_MSG "VCVTNH_U32_F16"
+#define INSN_NAME vcvtnh_u32_f16
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE uint32_t
+#define OUTPUT_TYPE_SIZE 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c
new file mode 100644
index 0000000..105d236
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_s32_f16_1.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected[] =
+{
+  0x00000000,
+  0x00000000,
+  0x0000007c,
+  0xfffffdc8,
+  0xffffffde,
+  0x00000400,
+  0x00000297,
+  0x000000aa,
+  0xfffffffc,
+  0x0000004d,
+  0xffffff70,
+  0xffffffc8,
+  0xfffffff0,
+  0xfffffff1,
+  0xfffffff2,
+  0xfffffff3
+};
+
+#define TEST_MSG "VCVTPH_S32_F16"
+#define INSN_NAME vcvtph_s32_f16
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE int32_t
+#define OUTPUT_TYPE_SIZE 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c
new file mode 100644
index 0000000..d66adcd
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vcvtph_u32_f16_1.c
@@ -0,0 +1,53 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Input values.  */
+float16_t input[] =
+{
+  0.0, -0.0,
+  123.4, -567.8,
+  -34.8, 1024,
+  663.1, 169.1,
+  -4.8, 77.0,
+  -144.5, -56.8,
+
+  (float16_t) -16, (float16_t) -15,
+  (float16_t) -14, (float16_t) -13,
+};
+
+/* Expected results (32-bit hexadecimal representation).  */
+uint32_t expected[] =
+{
+  0x00000000,
+  0x00000000,
+  0x0000007c,
+  0x00000000,
+  0x00000000,
+  0x00000400,
+  0x00000297,
+  0x000000aa,
+  0x00000000,
+  0x0000004d,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+  0x00000000,
+};
+
+#define TEST_MSG "VCVTPH_U32_F16"
+#define INSN_NAME vcvtph_u32_f16
+
+#define INPUT input
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE uint32_t
+#define OUTPUT_TYPE_SIZE 32
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c
new file mode 100644
index 0000000..6a99109
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vdivh_f16_1.c
@@ -0,0 +1,42 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+#define INFF __builtin_inf ()
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0xb765 /* -0.462158 */,
+  0x27ef /* 0.030991 */,
+  0x3955 /* 0.666504 */,
+  0xccff /* -19.984375 */,
+  0xc49a /* -4.601562 */,
+  0xb1e3 /* -0.183960 */,
+  0x3cd3 /* 1.206055 */,
+  0x23f0 /* 0.015503 */,
+  0xa9ef /* -0.046356 */,
+  0x32f4 /* 0.217285 */,
+  0xb036 /* -0.131592 */,
+  0x4126 /* 2.574219 */,
+  0xcd15 /* -20.328125 */,
+  0x537f /* 59.968750 */,
+  0x7e00 /* nan */,
+  0x7e00 /* nan */
+};
+
+#define TEST_MSG "VDIVH_F16"
+#define INSN_NAME vdivh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for binary scalar operations.  */
+#include "binary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c
new file mode 100644
index 0000000..1ac6b67
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmah_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+ 0x0000 /* 0.000000 */,
+ 0x0000 /* 0.000000 */,
+ 0x3944 /* 0.658203 */,
+ 0xcefa /* -27.906250 */,
+ 0x5369 /* 59.281250 */,
+ 0x35ba /* 0.357910 */,
+ 0xc574 /* -5.453125 */,
+ 0xc5e6 /* -5.898438 */,
+ 0x3f66 /* 1.849609 */,
+ 0x5665 /* 102.312500 */,
+ 0xc02d /* -2.087891 */,
+ 0x4d79 /* 21.890625 */,
+ 0x547b /* 71.687500 */,
+ 0xcdf0 /* -23.750000 */,
+ 0xc625 /* -6.144531 */,
+ 0x4cf9 /* 19.890625 */,
+ 0x7e00 /* nan */,
+ 0x7e00 /* nan */
+};
+
+#define TEST_MSG "VFMAH_F16"
+#define INSN_NAME vfmah_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for binary scalar operations.  */
+#include "ternary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c
new file mode 100644
index 0000000..77021be
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vfmsh_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0x42af /* 3.341797 */,
+  0x5043 /* 34.093750 */,
+  0xccd2 /* -19.281250 */,
+  0x3712 /* 0.441895 */,
+  0x3acc /* 0.849609 */,
+  0x4848 /* 8.562500 */,
+  0xcc43 /* -17.046875 */,
+  0xd65c /* -101.750000 */,
+  0x4185 /* 2.759766 */,
+  0xcd39 /* -20.890625 */,
+  0xd45b /* -69.687500 */,
+  0x5241 /* 50.031250 */,
+  0xc675 /* -6.457031 */,
+  0x4d07 /* 20.109375 */,
+  0x7c00 /* inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VFMSH_F16"
+#define INSN_NAME vfmsh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for binary scalar operations.  */
+#include "ternary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c
new file mode 100644
index 0000000..4db4b84
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmaxnmh_f16_1.c
@@ -0,0 +1,42 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+#define INFF __builtin_inf ()
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x4000 /* 2.000000 */,
+  0x5640 /* 100.000000 */,
+  0x4f80 /* 30.000000 */,
+  0x3666 /* 0.399902 */,
+  0x3800 /* 0.500000 */,
+  0x3d52 /* 1.330078 */,
+  0xc64d /* -6.300781 */,
+  0x4d00 /* 20.000000 */,
+  0x355d /* 0.335205 */,
+  0x409a /* 2.300781 */,
+  0x3c00 /* 1.000000 */,
+  0x4a91 /* 13.132812 */,
+  0x34f6 /* 0.310059 */,
+  0x4d00 /* 20.000000 */,
+  0x7c00 /* inf */,
+  0x7c00 /* inf */
+};
+
+#define TEST_MSG "VMAXNMH_F16"
+#define INSN_NAME vmaxnmh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for binary scalar operations.  */
+#include "binary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c
new file mode 100644
index 0000000..f6b0216
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vminnmh_f16_1.c
@@ -0,0 +1,42 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+#define INFF __builtin_inf ()
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0xc454 /* -4.328125 */,
+  0x4233 /* 3.099609 */,
+  0x4d00 /* 20.000000 */,
+  0xa51f /* -0.020004 */,
+  0xc09a /* -2.300781 */,
+  0xc73b /* -7.230469 */,
+  0xc79a /* -7.601562 */,
+  0x34f6 /* 0.310059 */,
+  0xc73b /* -7.230469 */,
+  0x3800 /* 0.500000 */,
+  0xc79a /* -7.601562 */,
+  0x451a /* 5.101562 */,
+  0xc64d /* -6.300781 */,
+  0x3556 /* 0.333496 */,
+  0xfc00 /* -inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VMINNMH_F16"
+#define INSN_NAME vminnmh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for binary scalar operations.  */
+#include "binary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c
new file mode 100644
index 0000000..09684d2
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vmulh_f16_1.c
@@ -0,0 +1,42 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+#define INFF __builtin_inf ()
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0xc854 /* -8.656250 */,
+  0x5cd8 /* 310.000000 */,
+  0x60b0 /* 600.000000 */,
+  0xa019 /* -0.008003 */,
+  0xbc9a /* -1.150391 */,
+  0xc8cf /* -9.617188 */,
+  0x51fd /* 47.906250 */,
+  0x4634 /* 6.203125 */,
+  0xc0d9 /* -2.423828 */,
+  0x3c9a /* 1.150391 */,
+  0xc79a /* -7.601562 */,
+  0x5430 /* 67.000000 */,
+  0xbfd0 /* -1.953125 */,
+  0x46ac /* 6.671875 */,
+  0xfc00 /* -inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VMULH_F16"
+#define INSN_NAME vmulh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for binary scalar operations.  */
+#include "binary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c
new file mode 100644
index 0000000..421d827
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vnegh_f16_1.c
@@ -0,0 +1,39 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+uint16_t expected[] =
+{
+  0x8000 /* -0.000000 */,
+  0x0000 /* 0.000000 */,
+  0xc000 /* -2.000000 */,
+  0xc233 /* -3.099609 */,
+  0xcd00 /* -20.000000 */,
+  0xb666 /* -0.399902 */,
+  0x409a /* 2.300781 */,
+  0xbd52 /* -1.330078 */,
+  0x479a /* 7.601562 */,
+  0xb4f6 /* -0.310059 */,
+  0xb55d /* -0.335205 */,
+  0xb800 /* -0.500000 */,
+  0xbc00 /* -1.000000 */,
+  0xca91 /* -13.132812 */,
+  0x464d /* 6.300781 */,
+  0xcd00 /* -20.000000 */,
+  0xfc00 /* -inf */,
+  0x7c00 /* inf */
+};
+
+#define TEST_MSG "VNEGH_F16"
+#define INSN_NAME vnegh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c
new file mode 100644
index 0000000..bcf47f6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndah_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0x4000 /* 2.000000 */,
+  0x4200 /* 3.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x0000 /* 0.000000 */,
+  0xc000 /* -2.000000 */,
+  0x3c00 /* 1.000000 */,
+  0xc800 /* -8.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x4a80 /* 13.000000 */,
+  0xc600 /* -6.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x7c00 /* inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VRNDAH_F16"
+#define INSN_NAME vrndah_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c
new file mode 100644
index 0000000..3c4649e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndh_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0x4000 /* 2.000000 */,
+  0x4200 /* 3.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x0000 /* 0.000000 */,
+  0xc000 /* -2.000000 */,
+  0x3c00 /* 1.000000 */,
+  0xc700 /* -7.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x4a80 /* 13.000000 */,
+  0xc600 /* -6.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x7c00 /* inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VRNDH_F16"
+#define INSN_NAME vrndh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c
new file mode 100644
index 0000000..4a7b721
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndih_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0x4000 /* 2.000000 */,
+  0x4200 /* 3.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x0000 /* 0.000000 */,
+  0xc000 /* -2.000000 */,
+  0x3c00 /* 1.000000 */,
+  0xc800 /* -8.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x4a80 /* 13.000000 */,
+  0xc600 /* -6.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x7c00 /* inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VRNDIH_F16"
+#define INSN_NAME vrndih_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c
new file mode 100644
index 0000000..9af357d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndmh_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0x4000 /* 2.000000 */,
+  0x4200 /* 3.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x0000 /* 0.000000 */,
+  0xc200 /* -3.000000 */,
+  0x3c00 /* 1.000000 */,
+  0xc800 /* -8.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x4a80 /* 13.000000 */,
+  0xc700 /* -7.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x7c00 /* inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VRNDMH_F16"
+#define INSN_NAME vrndmh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c
new file mode 100644
index 0000000..eb4b27d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndnh_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0x4000 /* 2.000000 */,
+  0x4200 /* 3.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x0000 /* 0.000000 */,
+  0xc000 /* -2.000000 */,
+  0x3c00 /* 1.000000 */,
+  0xc800 /* -8.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x4a80 /* 13.000000 */,
+  0xc600 /* -6.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x7c00 /* inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VRNDNH_F16"
+#define INSN_NAME vrndnh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c
new file mode 100644
index 0000000..3fa9749
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndph_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0x4000 /* 2.000000 */,
+  0x4400 /* 4.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x3c00 /* 1.000000 */,
+  0xc000 /* -2.000000 */,
+  0x4000 /* 2.000000 */,
+  0xc700 /* -7.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x4b00 /* 14.000000 */,
+  0xc600 /* -6.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x7c00 /* inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VRNDPH_F16"
+#define INSN_NAME vrndph_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c
new file mode 100644
index 0000000..eb4b27d
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vrndxh_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0x4000 /* 2.000000 */,
+  0x4200 /* 3.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x0000 /* 0.000000 */,
+  0xc000 /* -2.000000 */,
+  0x3c00 /* 1.000000 */,
+  0xc800 /* -8.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x0000 /* 0.000000 */,
+  0x3c00 /* 1.000000 */,
+  0x4a80 /* 13.000000 */,
+  0xc600 /* -6.000000 */,
+  0x4d00 /* 20.000000 */,
+  0x7c00 /* inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VRNDNH_F16"
+#define INSN_NAME vrndnh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c
new file mode 100644
index 0000000..7d03827
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsqrth_f16_1.c
@@ -0,0 +1,40 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0x0000 /* 0.000000 */,
+  0x8000 /* -0.000000 */,
+  0x3da8 /* 1.414062 */,
+  0x3f0b /* 1.760742 */,
+  0x4479 /* 4.472656 */,
+  0x390f /* 0.632324 */,
+  0x7e00 /* nan */,
+  0x3c9d /* 1.153320 */,
+  0x7e00 /* nan */,
+  0x3874 /* 0.556641 */,
+  0x38a2 /* 0.579102 */,
+  0x39a8 /* 0.707031 */,
+  0x3c00 /* 1.000000 */,
+  0x433f /* 3.623047 */,
+  0x7e00 /* nan */,
+  0x4479 /* 4.472656 */,
+  0x7c00 /* inf */,
+  0x7e00 /* nan */
+};
+
+#define TEST_MSG "VSQRTH_F16"
+#define INSN_NAME vsqrth_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for unary scalar operations.  */
+#include "unary_scalar_op.inc"
diff --git a/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c
new file mode 100644
index 0000000..a7aba11
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/advsimd-intrinsics/vsubh_f16_1.c
@@ -0,0 +1,42 @@ 
+/* { dg-do run } */
+/* { dg-require-effective-target arm_v8_2a_fp16_scalar_hw } */
+/* { dg-add-options arm_v8_2a_fp16_scalar }  */
+
+#include <arm_fp16.h>
+
+#define INFF __builtin_inf ()
+
+/* Expected results (16-bit hexadecimal representation).  */
+uint16_t expected[] =
+{
+  0xbc00 /* -1.000000 */,
+  0xbc00 /* -1.000000 */,
+  0x4654 /* 6.328125 */,
+  0xd60e /* -96.875000 */,
+  0xc900 /* -10.000000 */,
+  0x36b8 /* 0.419922 */,
+  0xc19a /* -2.800781 */,
+  0x4848 /* 8.562500 */,
+  0xbd34 /* -1.300781 */,
+  0xccec /* -19.687500 */,
+  0x4791 /* 7.566406 */,
+  0xbf34 /* -1.800781 */,
+  0x484d /* 8.601562 */,
+  0x4804 /* 8.031250 */,
+  0xc69c /* -6.609375 */,
+  0x4ceb /* 19.671875 */,
+  0x7c00 /* inf */,
+  0xfc00 /* -inf */
+};
+
+#define TEST_MSG "VSUB_F16"
+#define INSN_NAME vsubh_f16
+
+#define EXPECTED expected
+
+#define INPUT_TYPE float16_t
+#define OUTPUT_TYPE float16_t
+#define OUTPUT_TYPE_SIZE 16
+
+/* Include the template for binary scalar operations.  */
+#include "binary_scalar_op.inc"
-- 
2.1.4