| Message ID | 1467405303-19212-1-git-send-email-stefan@shauser.net |
|---|---|
| State | Accepted, archived |
| Delegated to: | David Miller |
| Headers | show |
Le 01/07/2016 13:35, Stefan Hauser a écrit : > When initializing the PHY control register, the FIFO depth bits are > written without reading the previous register value, i.e. all other > bits are overwritten with zero. This disables automatic MDI-X > configuration, which is enabled by default. Fix initialization by doing > a read/modify/write operation. > > Signed-off-by: Stefan Hauser <stefan@shauser.net> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Fixes: 2a10154abcb7 ("net: phy: dp83867: Add TI dp83867 phy")
From: Stefan Hauser <stefan@shauser.net> Date: Fri, 1 Jul 2016 22:35:03 +0200 > When initializing the PHY control register, the FIFO depth bits are > written without reading the previous register value, i.e. all other > bits are overwritten with zero. This disables automatic MDI-X > configuration, which is enabled by default. Fix initialization by doing > a read/modify/write operation. > > Signed-off-by: Stefan Hauser <stefan@shauser.net> Applied.
diff --git a/drivers/net/phy/dp83867.c b/drivers/net/phy/dp83867.c index 2afa61b..91177a4 100644 --- a/drivers/net/phy/dp83867.c +++ b/drivers/net/phy/dp83867.c @@ -57,6 +57,7 @@ /* PHY CTRL bits */ #define DP83867_PHYCR_FIFO_DEPTH_SHIFT 14 +#define DP83867_PHYCR_FIFO_DEPTH_MASK (3 << 14) /* RGMIIDCTL bits */ #define DP83867_RGMII_TX_CLK_DELAY_SHIFT 4 @@ -133,8 +134,8 @@ static int dp83867_of_init(struct phy_device *phydev) static int dp83867_config_init(struct phy_device *phydev) { struct dp83867_private *dp83867; - int ret; - u16 val, delay; + int ret, val; + u16 delay; if (!phydev->priv) { dp83867 = devm_kzalloc(&phydev->mdio.dev, sizeof(*dp83867), @@ -151,8 +152,12 @@ static int dp83867_config_init(struct phy_device *phydev) } if (phy_interface_is_rgmii(phydev)) { - ret = phy_write(phydev, MII_DP83867_PHYCTRL, - (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT)); + val = phy_read(phydev, MII_DP83867_PHYCTRL); + if (val < 0) + return val; + val &= ~DP83867_PHYCR_FIFO_DEPTH_MASK; + val |= (dp83867->fifo_depth << DP83867_PHYCR_FIFO_DEPTH_SHIFT); + ret = phy_write(phydev, MII_DP83867_PHYCTRL, val); if (ret) return ret; }
When initializing the PHY control register, the FIFO depth bits are written without reading the previous register value, i.e. all other bits are overwritten with zero. This disables automatic MDI-X configuration, which is enabled by default. Fix initialization by doing a read/modify/write operation. Signed-off-by: Stefan Hauser <stefan@shauser.net> --- drivers/net/phy/dp83867.c | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-)