diff mbox

, Fix PowerPC PR target/71720 (bad vec_init of V4SF on power9)

Message ID 20160701001041.GA20734@ibm-tiger.the-meissners.org
State New
Headers show

Commit Message

Michael Meissner July 1, 2016, 12:10 a.m. UTC 
Aaron Sawdey was running tests on the Power9 simulator, and he noticed that the
XXSPLTW to splat the SFmode value into the vector accessed the wrong element.
When I added the more general code for vector splat for power9, I called an
insn that reversed the element numbers on little endian, when I should have
called the direct function, since the XSCVDPSPN instruction leaves the
converted value in real element 0 in the hardware.

I did a bootstrap and make check with no regressions, can I check this into the
trunk?  And can I back port the patch to GCC 6.2 after a burn-in period?

[gcc]
2016-06-30  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71720
	* config/rs6000/vsx.md (vsx_splat_v4sf_internal): When splitting
	the insns, use vsx_xxspltw_v4sf_direct which does not check for
	little endian.

[gcc/testsuite]
2016-06-30  Michael Meissner  <meissner@linux.vnet.ibm.com>

	PR target/71720
	* gcc.target/powerpc/pr71720.c: New test.
diff mbox

Patch

Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md	(revision 237895)
+++ gcc/config/rs6000/vsx.md	(working copy)
@@ -2512,9 +2512,8 @@  (define_insn_and_split "*vsx_splat_v4sf_
   [(set (match_dup 0)
 	(unspec:V4SF [(match_dup 1)] UNSPEC_VSX_CVDPSPN))
    (set (match_dup 0)
-	(vec_duplicate:V4SF
-	 (vec_select:SF (match_dup 0)
-			(parallel [(const_int 0)]))))]
+	(unspec:V4SF [(match_dup 0)
+		      (const_int 0)] UNSPEC_VSX_XXSPLTW))]
   ""
   [(set_attr "type" "vecload,vecperm,mftgpr")
    (set_attr "length" "4,8,4")])
Index: gcc/testsuite/gcc.target/powerpc/pr71720.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/pr71720.c	(revision 0)
+++ gcc/testsuite/gcc.target/powerpc/pr71720.c	(working copy)
@@ -0,0 +1,15 @@ 
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+/* { dg-options "-mcpu=power9 -O2 -mupper-regs-di" } */
+
+/* Verify that we generate xxspltw <reg>,<reg>,0 for V4SFmode splat.  */
+
+vector float
+splat_v4sf (float f)
+{
+  return (vector float) { f, f, f, f };
+}
+
+/* { dg-final { scan-assembler "xscvdpspn "      } } */
+/* { dg-final { scan-assembler "xxspltw .*,.*,0" } } */