| Message ID | 1467138270-32481-10-git-send-email-clg@kaod.org |
|---|---|
| State | New |
| Headers | show |
On 28 June 2016 at 19:24, Cédric Le Goater <clg@kaod.org> wrote: > This test uses the palmetto platform and the AST2400 SPI controller to > test the m25p80 flash module device model. The flash model is defined > by the platform (n25q256a) and it would be nice to find way to control > it, using a property probably. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > --- > This test fails on ppc64be: TEST: tests/m25p80-test... (pid=65123) /arm/m25p80/read_jedec: OK /arm/m25p80/erase_sector: OK /arm/m25p80/erase_all: ** ERROR:/home/pm215/qemu/tests/m25p80-test.c:162:test_erase_all: assertion failed (page[i] == 0x0): (0xffffffff == 0x00000000) FAIL GTester: last random seed: R02S54b2016fda21b092e18d7a23a2db86ba (pid=65128) /arm/m25p80/write_page: ** ERROR:/home/pm215/qemu/tests/m25p80-test.c:200:test_write_page: assertion failed (page[i] == my_page_addr + i * 4): (0x00000000 == 0x01400000) FAIL GTester: last random seed: R02S8708910d6b72f700bc41e9340a516239 (pid=65133) FAIL: tests/m25p80-test thanks -- PMM
On 1 July 2016 at 18:18, Peter Maydell <peter.maydell@linaro.org> wrote: > On 28 June 2016 at 19:24, Cédric Le Goater <clg@kaod.org> wrote: >> This test uses the palmetto platform and the AST2400 SPI controller to >> test the m25p80 flash module device model. The flash model is defined >> by the platform (n25q256a) and it would be nice to find way to control >> it, using a property probably. >> >> Signed-off-by: Cédric Le Goater <clg@kaod.org> >> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> >> --- >> > > This test fails on ppc64be: > > TEST: tests/m25p80-test... (pid=65123) > /arm/m25p80/read_jedec: OK > /arm/m25p80/erase_sector: OK > /arm/m25p80/erase_all: ** > ERROR:/home/pm215/qemu/tests/m25p80-test.c:162:test_erase_all: > assertion failed (page[i] == 0x0): > (0xffffffff == 0x00000000) > FAIL > GTester: last random seed: R02S54b2016fda21b092e18d7a23a2db86ba > (pid=65128) > /arm/m25p80/write_page: ** > ERROR:/home/pm215/qemu/tests/m25p80-test.c:200:test_write_page: > assertion failed (page[i] == my_page_addr + i * 4): (0x00000000 == > 0x01400000) > FAIL > GTester: last random seed: R02S8708910d6b72f700bc41e9340a516239 > (pid=65133) > FAIL: tests/m25p80-test I'm going to take the easy approach of just dropping this patch; please fix and resend it. thanks -- PMM
On 07/01/2016 07:18 PM, Peter Maydell wrote: > On 28 June 2016 at 19:24, Cédric Le Goater <clg@kaod.org> wrote: >> This test uses the palmetto platform and the AST2400 SPI controller to >> test the m25p80 flash module device model. The flash model is defined >> by the platform (n25q256a) and it would be nice to find way to control >> it, using a property probably. >> >> Signed-off-by: Cédric Le Goater <clg@kaod.org> >> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> >> --- >> > > This test fails on ppc64be: > > TEST: tests/m25p80-test... (pid=65123) > /arm/m25p80/read_jedec: OK > /arm/m25p80/erase_sector: OK > /arm/m25p80/erase_all: ** > ERROR:/home/pm215/qemu/tests/m25p80-test.c:162:test_erase_all: > assertion failed (page[i] == 0x0): > (0xffffffff == 0x00000000) > FAIL > GTester: last random seed: R02S54b2016fda21b092e18d7a23a2db86ba > (pid=65128) > /arm/m25p80/write_page: ** > ERROR:/home/pm215/qemu/tests/m25p80-test.c:200:test_write_page: > assertion failed (page[i] == my_page_addr + i * 4): (0x00000000 == > 0x01400000) > FAIL > GTester: last random seed: R02S8708910d6b72f700bc41e9340a516239 > (pid=65133) > FAIL: tests/m25p80-test yes ... I am not sure how to fix this :/ I started with a patch using qtest_big_endian() and I found that this one was fixing the problem : https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg07876.html but it feels wrong. The interesting part is that the guest fully boots on a ppc64be. We need an endian shaman for this. Greg ? Thanks, C.
On Fri, 1 Jul 2016 19:30:30 +0200 Cédric Le Goater <clg@kaod.org> wrote: > On 07/01/2016 07:18 PM, Peter Maydell wrote: > > On 28 June 2016 at 19:24, Cédric Le Goater <clg@kaod.org> wrote: > >> This test uses the palmetto platform and the AST2400 SPI controller to > >> test the m25p80 flash module device model. The flash model is defined > >> by the platform (n25q256a) and it would be nice to find way to control > >> it, using a property probably. > >> > >> Signed-off-by: Cédric Le Goater <clg@kaod.org> > >> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > >> --- > >> > > > > This test fails on ppc64be: > > > > TEST: tests/m25p80-test... (pid=65123) > > /arm/m25p80/read_jedec: OK > > /arm/m25p80/erase_sector: OK > > /arm/m25p80/erase_all: ** > > ERROR:/home/pm215/qemu/tests/m25p80-test.c:162:test_erase_all: > > assertion failed (page[i] == 0x0): > > (0xffffffff == 0x00000000) > > FAIL > > GTester: last random seed: R02S54b2016fda21b092e18d7a23a2db86ba > > (pid=65128) > > /arm/m25p80/write_page: ** > > ERROR:/home/pm215/qemu/tests/m25p80-test.c:200:test_write_page: > > assertion failed (page[i] == my_page_addr + i * 4): (0x00000000 == > > 0x01400000) > > FAIL > > GTester: last random seed: R02S8708910d6b72f700bc41e9340a516239 > > (pid=65133) > > FAIL: tests/m25p80-test > > yes ... I am not sure how to fix this :/ > > I started with a patch using qtest_big_endian() and I found that > this one was fixing the problem : > > https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg07876.html > > but it feels wrong. The interesting part is that the guest fully > boots on a ppc64be. We need an endian shaman for this. Greg ? > Heh ! Looking at the Cc list I guess you have chances to find the shaman you're looking for :) Anyway, doing bswap32() systematically like in the patch mentioned above looks weird indeed. > Thanks, > > C.
W dniu 28.06.2016 o 20:24, Cédric Le Goater pisze: > This test uses the palmetto platform and the AST2400 SPI controller to > test the m25p80 flash module device model. The flash model is defined > by the platform (n25q256a) and it would be nice to find way to control > it, using a property probably. > > Signed-off-by: Cédric Le Goater <clg@kaod.org> > Reviewed-by: Peter Maydell <peter.maydell@linaro.org> > --- > > Changes since v4: > > - fixed Makefile targets > - replaced -M with -m in qtest command line > > Changes since v2: > > - changed mkstemp() path prefix > > Changes since v1: > > - fixed guest args to use -drive and not -mtdblock > > tests/Makefile.include | 2 + > tests/m25p80-test.c | 242 +++++++++++++++++++++++++++++++++++++++++++++++++ > 2 files changed, 244 insertions(+) > create mode 100644 tests/m25p80-test.c > > diff --git a/tests/Makefile.include b/tests/Makefile.include > index 6c09962f7581..149f92585c1b 100644 > --- a/tests/Makefile.include > +++ b/tests/Makefile.include > @@ -252,6 +252,7 @@ gcov-files-sparc-y += hw/timer/m48t59.c > gcov-files-sparc64-y += hw/timer/m48t59.c > check-qtest-arm-y = tests/tmp105-test$(EXESUF) > check-qtest-arm-y += tests/ds1338-test$(EXESUF) > +check-qtest-arm-y += tests/m25p80-test$(EXESUF) > gcov-files-arm-y += hw/misc/tmp105.c > check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) > gcov-files-arm-y += arm-softmmu/hw/block/virtio-blk.c > @@ -568,6 +569,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \ > tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y) > tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) > tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) > +tests/m25p80-test$(EXESUF): tests/m25p80-test.o > tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) > tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) > tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y) > diff --git a/tests/m25p80-test.c b/tests/m25p80-test.c > new file mode 100644 > index 000000000000..305c52319a33 > --- /dev/null > +++ b/tests/m25p80-test.c > @@ -0,0 +1,242 @@ > +/* > + * QTest testcase for the M25P80 Flash (Using the AST2400 SPI Controller) > + * > + * Copyright (C) 2016 IBM Corp. > + * > + * Permission is hereby granted, free of charge, to any person obtaining a copy > + * of this software and associated documentation files (the "Software"), to deal > + * in the Software without restriction, including without limitation the rights > + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell > + * copies of the Software, and to permit persons to whom the Software is > + * furnished to do so, subject to the following conditions: > + * > + * The above copyright notice and this permission notice shall be included in > + * all copies or substantial portions of the Software. > + * > + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR > + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, > + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL > + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER > + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, > + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN > + * THE SOFTWARE. > + */ > + > +#include "qemu/osdep.h" > +#include "qemu/bswap.h" > +#include "libqtest.h" > + > +/* > + * AST2400 SPI Controller registers > + */ > +#define R_CONF 0x00 > +#define CONF_ENABLE_W0 (1 << 16) > +#define R_CE_CTRL 0x04 > +#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ > +#define R_CTRL0 0x10 > +#define CTRL_CE_STOP_ACTIVE (1 << 2) > +#define CTRL_USERMODE 0x3 > + > +#define AST2400_FMC_BASE 0x1E620000 > +#define AST2400_FLASH_BASE 0x20000000 > + > +/* > + * Flash commands > + */ > +enum { > + JEDEC_READ = 0x9f, > + BULK_ERASE = 0xc7, > + READ = 0x03, > + PP = 0x02, > + WREN = 0x6, > + EN_4BYTE_ADDR = 0xB7, > + ERASE_SECTOR = 0xd8, > +}; > + > +#define FLASH_JEDEC 0x20ba19 /* n25q256a */ > +#define FLASH_SIZE (32 * 1024 * 1024) > + > +#define PAGE_SIZE 256 > + > +static void spi_conf(uint32_t value) > +{ > + uint32_t conf = readl(AST2400_FMC_BASE + R_CONF); > + > + conf |= value; > + writel(AST2400_FMC_BASE + R_CONF, conf); > +} > + > +static void spi_ctrl_start_user(void) > +{ > + uint32_t ctrl = readl(AST2400_FMC_BASE + R_CTRL0); > + > + ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; > + writel(AST2400_FMC_BASE + R_CTRL0, ctrl); > + > + ctrl &= ~CTRL_CE_STOP_ACTIVE; > + writel(AST2400_FMC_BASE + R_CTRL0, ctrl); > +} > + > +static void spi_ctrl_stop_user(void) > +{ > + uint32_t ctrl = readl(AST2400_FMC_BASE + R_CTRL0); > + > + ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; > + writel(AST2400_FMC_BASE + R_CTRL0, ctrl); > +} > + > +static void test_read_jedec(void) > +{ > + uint32_t jedec = 0x0; > + > + spi_conf(CONF_ENABLE_W0); > + > + spi_ctrl_start_user(); > + writeb(AST2400_FLASH_BASE, JEDEC_READ); > + jedec |= readb(AST2400_FLASH_BASE) << 16; > + jedec |= readb(AST2400_FLASH_BASE) << 8; > + jedec |= readb(AST2400_FLASH_BASE); > + spi_ctrl_stop_user(); > + > + g_assert_cmphex(jedec, ==, FLASH_JEDEC); > +} > + > +static void read_page(uint32_t addr, uint32_t *page) > +{ > + int i; > + > + spi_ctrl_start_user(); > + > + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); > + writeb(AST2400_FLASH_BASE, READ); > + writel(AST2400_FLASH_BASE, cpu_to_be32(addr)); > + > + /* Continuous read are supported */ > + for (i = 0; i < PAGE_SIZE / 4; i++) { > + page[i] = be32_to_cpu(readl(AST2400_FLASH_BASE)); > + } > + spi_ctrl_stop_user(); > +} > + > +static void test_erase_sector(void) > +{ > + uint32_t some_page_addr = 0x600 * PAGE_SIZE; > + uint32_t page[PAGE_SIZE / 4]; > + int i; > + > + spi_conf(CONF_ENABLE_W0); > + > + spi_ctrl_start_user(); > + writeb(AST2400_FLASH_BASE, WREN); > + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); > + writeb(AST2400_FLASH_BASE, ERASE_SECTOR); > + writel(AST2400_FLASH_BASE, cpu_to_be32(some_page_addr)); Hi, I think you should not make any byte swapping because qtest for all write* instructions (see qtest.c:377). Regards, Marcin > + spi_ctrl_stop_user(); > + > + /* Previous page should be full of zeroes as backend is not > + * initialized */ > + read_page(some_page_addr - PAGE_SIZE, page); > + for (i = 0; i < PAGE_SIZE / 4; i++) { > + g_assert_cmphex(page[i], ==, 0x0); > + } > + > + /* But this one was erased */ > + read_page(some_page_addr, page); > + for (i = 0; i < PAGE_SIZE / 4; i++) { > + g_assert_cmphex(page[i], ==, 0xffffffff); > + } > +} > + > +static void test_erase_all(void) > +{ > + uint32_t some_page_addr = 0x15000 * PAGE_SIZE; > + uint32_t page[PAGE_SIZE / 4]; > + int i; > + > + spi_conf(CONF_ENABLE_W0); > + > + /* Check some random page. Should be full of zeroes as backend is > + * not initialized */ > + read_page(some_page_addr, page); > + for (i = 0; i < PAGE_SIZE / 4; i++) { > + g_assert_cmphex(page[i], ==, 0x0); > + } > + > + spi_ctrl_start_user(); > + writeb(AST2400_FLASH_BASE, WREN); > + writeb(AST2400_FLASH_BASE, BULK_ERASE); > + spi_ctrl_stop_user(); > + > + /* Recheck that some random page */ > + read_page(some_page_addr, page); > + for (i = 0; i < PAGE_SIZE / 4; i++) { > + g_assert_cmphex(page[i], ==, 0xffffffff); > + } > +} > + > +static void test_write_page(void) > +{ > + uint32_t my_page_addr = 0x14000 * PAGE_SIZE; /* beyond 16MB */ > + uint32_t some_page_addr = 0x15000 * PAGE_SIZE; > + uint32_t page[PAGE_SIZE / 4]; > + int i; > + > + spi_conf(CONF_ENABLE_W0); > + > + spi_ctrl_start_user(); > + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); > + writeb(AST2400_FLASH_BASE, PP); > + writel(AST2400_FLASH_BASE, cpu_to_be32(my_page_addr)); > + > + /* Fill the page with its own addresses */ > + for (i = 0; i < PAGE_SIZE / 4; i++) { > + writel(AST2400_FLASH_BASE, cpu_to_be32(my_page_addr + i * 4)); > + } > + spi_ctrl_stop_user(); > + > + /* Check what was written */ > + read_page(my_page_addr, page); > + for (i = 0; i < PAGE_SIZE / 4; i++) { > + g_assert_cmphex(page[i], ==, my_page_addr + i * 4); > + } > + > + /* Check some other page. It should be full of 0xff */ > + read_page(some_page_addr, page); > + for (i = 0; i < PAGE_SIZE / 4; i++) { > + g_assert_cmphex(page[i], ==, 0xffffffff); > + } > +} > + > +static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX"; > + > +int main(int argc, char **argv) > +{ > + int ret; > + int fd; > + char *args; > + > + g_test_init(&argc, &argv, NULL); > + > + fd = mkstemp(tmp_path); > + g_assert(fd >= 0); > + ret = ftruncate(fd, FLASH_SIZE); > + g_assert(ret == 0); > + close(fd); > + > + args = g_strdup_printf("-m 256 -machine palmetto-bmc " > + "-drive file=%s,format=raw,if=mtd", > + tmp_path); > + qtest_start(args); > + > + qtest_add_func("/m25p80/read_jedec", test_read_jedec); > + qtest_add_func("/m25p80/erase_sector", test_erase_sector); > + qtest_add_func("/m25p80/erase_all", test_erase_all); > + qtest_add_func("/m25p80/write_page", test_write_page); > + > + ret = g_test_run(); > + > + qtest_quit(global_qtest); > + unlink(tmp_path); > + g_free(args); > + return ret; > +}
On 07/02/2016 08:05 PM, mar.krzeminski wrote: > > > W dniu 28.06.2016 o 20:24, Cédric Le Goater pisze: >> This test uses the palmetto platform and the AST2400 SPI controller to >> test the m25p80 flash module device model. The flash model is defined >> by the platform (n25q256a) and it would be nice to find way to control >> it, using a property probably. >> >> Signed-off-by: Cédric Le Goater <clg@kaod.org> >> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> >> --- >> >> Changes since v4: >> >> - fixed Makefile targets >> - replaced -M with -m in qtest command line >> Changes since v2: >> >> - changed mkstemp() path prefix >> Changes since v1: >> >> - fixed guest args to use -drive and not -mtdblock >> >> tests/Makefile.include | 2 + >> tests/m25p80-test.c | 242 +++++++++++++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 244 insertions(+) >> create mode 100644 tests/m25p80-test.c >> >> diff --git a/tests/Makefile.include b/tests/Makefile.include >> index 6c09962f7581..149f92585c1b 100644 >> --- a/tests/Makefile.include >> +++ b/tests/Makefile.include >> @@ -252,6 +252,7 @@ gcov-files-sparc-y += hw/timer/m48t59.c >> gcov-files-sparc64-y += hw/timer/m48t59.c >> check-qtest-arm-y = tests/tmp105-test$(EXESUF) >> check-qtest-arm-y += tests/ds1338-test$(EXESUF) >> +check-qtest-arm-y += tests/m25p80-test$(EXESUF) >> gcov-files-arm-y += hw/misc/tmp105.c >> check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) >> gcov-files-arm-y += arm-softmmu/hw/block/virtio-blk.c >> @@ -568,6 +569,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \ >> tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y) >> tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) >> tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) >> +tests/m25p80-test$(EXESUF): tests/m25p80-test.o >> tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) >> tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) >> tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y) >> diff --git a/tests/m25p80-test.c b/tests/m25p80-test.c >> new file mode 100644 >> index 000000000000..305c52319a33 >> --- /dev/null >> +++ b/tests/m25p80-test.c >> @@ -0,0 +1,242 @@ >> +/* >> + * QTest testcase for the M25P80 Flash (Using the AST2400 SPI Controller) >> + * >> + * Copyright (C) 2016 IBM Corp. >> + * >> + * Permission is hereby granted, free of charge, to any person obtaining a copy >> + * of this software and associated documentation files (the "Software"), to deal >> + * in the Software without restriction, including without limitation the rights >> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell >> + * copies of the Software, and to permit persons to whom the Software is >> + * furnished to do so, subject to the following conditions: >> + * >> + * The above copyright notice and this permission notice shall be included in >> + * all copies or substantial portions of the Software. >> + * >> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR >> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, >> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL >> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER >> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, >> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN >> + * THE SOFTWARE. >> + */ >> + >> +#include "qemu/osdep.h" >> +#include "qemu/bswap.h" >> +#include "libqtest.h" >> + >> +/* >> + * AST2400 SPI Controller registers >> + */ >> +#define R_CONF 0x00 >> +#define CONF_ENABLE_W0 (1 << 16) >> +#define R_CE_CTRL 0x04 >> +#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ >> +#define R_CTRL0 0x10 >> +#define CTRL_CE_STOP_ACTIVE (1 << 2) >> +#define CTRL_USERMODE 0x3 >> + >> +#define AST2400_FMC_BASE 0x1E620000 >> +#define AST2400_FLASH_BASE 0x20000000 >> + >> +/* >> + * Flash commands >> + */ >> +enum { >> + JEDEC_READ = 0x9f, >> + BULK_ERASE = 0xc7, >> + READ = 0x03, >> + PP = 0x02, >> + WREN = 0x6, >> + EN_4BYTE_ADDR = 0xB7, >> + ERASE_SECTOR = 0xd8, >> +}; >> + >> +#define FLASH_JEDEC 0x20ba19 /* n25q256a */ >> +#define FLASH_SIZE (32 * 1024 * 1024) >> + >> +#define PAGE_SIZE 256 >> + >> +static void spi_conf(uint32_t value) >> +{ >> + uint32_t conf = readl(AST2400_FMC_BASE + R_CONF); >> + >> + conf |= value; >> + writel(AST2400_FMC_BASE + R_CONF, conf); >> +} >> + >> +static void spi_ctrl_start_user(void) >> +{ >> + uint32_t ctrl = readl(AST2400_FMC_BASE + R_CTRL0); >> + >> + ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; >> + writel(AST2400_FMC_BASE + R_CTRL0, ctrl); >> + >> + ctrl &= ~CTRL_CE_STOP_ACTIVE; >> + writel(AST2400_FMC_BASE + R_CTRL0, ctrl); >> +} >> + >> +static void spi_ctrl_stop_user(void) >> +{ >> + uint32_t ctrl = readl(AST2400_FMC_BASE + R_CTRL0); >> + >> + ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; >> + writel(AST2400_FMC_BASE + R_CTRL0, ctrl); >> +} >> + >> +static void test_read_jedec(void) >> +{ >> + uint32_t jedec = 0x0; >> + >> + spi_conf(CONF_ENABLE_W0); >> + >> + spi_ctrl_start_user(); >> + writeb(AST2400_FLASH_BASE, JEDEC_READ); >> + jedec |= readb(AST2400_FLASH_BASE) << 16; >> + jedec |= readb(AST2400_FLASH_BASE) << 8; >> + jedec |= readb(AST2400_FLASH_BASE); >> + spi_ctrl_stop_user(); >> + >> + g_assert_cmphex(jedec, ==, FLASH_JEDEC); >> +} >> + >> +static void read_page(uint32_t addr, uint32_t *page) >> +{ >> + int i; >> + >> + spi_ctrl_start_user(); >> + >> + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); >> + writeb(AST2400_FLASH_BASE, READ); >> + writel(AST2400_FLASH_BASE, cpu_to_be32(addr)); >> + >> + /* Continuous read are supported */ >> + for (i = 0; i < PAGE_SIZE / 4; i++) { >> + page[i] = be32_to_cpu(readl(AST2400_FLASH_BASE)); >> + } >> + spi_ctrl_stop_user(); >> +} >> + >> +static void test_erase_sector(void) >> +{ >> + uint32_t some_page_addr = 0x600 * PAGE_SIZE; >> + uint32_t page[PAGE_SIZE / 4]; >> + int i; >> + >> + spi_conf(CONF_ENABLE_W0); >> + >> + spi_ctrl_start_user(); >> + writeb(AST2400_FLASH_BASE, WREN); >> + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); >> + writeb(AST2400_FLASH_BASE, ERASE_SECTOR); >> + writel(AST2400_FLASH_BASE, cpu_to_be32(some_page_addr)); > Hi, > > I think you should not make any byte swapping because > qtest for all write* instructions (see qtest.c:377). yes. on a BE, we should not byte swap. When on a LE host, the cpu_to_be32() call in the test byte-swaps the address, tswap32() in qtest.c does nothing as the host endian and guest endian are in sync and so the address reaches the controller region in the expected order. When on a BE host, the cpu_to_be32() does nothing but tswap32() in qtest.c reverses the order and so the address reaches the controller region in the wrong order (LE). I see two possible fixes : 1 - replace the read* routines by out* (no tswap there) 2 - add an extra byteswap on BE hosts using qtest_big_endian() as in virtio-blk-test.c. see virtio_blk_fix_request() Thanks, C. > Regards, > Marcin > >> + spi_ctrl_stop_user(); >> + >> + /* Previous page should be full of zeroes as backend is not >> + * initialized */ >> + read_page(some_page_addr - PAGE_SIZE, page); >> + for (i = 0; i < PAGE_SIZE / 4; i++) { >> + g_assert_cmphex(page[i], ==, 0x0); >> + } >> + >> + /* But this one was erased */ >> + read_page(some_page_addr, page); >> + for (i = 0; i < PAGE_SIZE / 4; i++) { >> + g_assert_cmphex(page[i], ==, 0xffffffff); >> + } >> +} >> + >> +static void test_erase_all(void) >> +{ >> + uint32_t some_page_addr = 0x15000 * PAGE_SIZE; >> + uint32_t page[PAGE_SIZE / 4]; >> + int i; >> + >> + spi_conf(CONF_ENABLE_W0); >> + >> + /* Check some random page. Should be full of zeroes as backend is >> + * not initialized */ >> + read_page(some_page_addr, page); >> + for (i = 0; i < PAGE_SIZE / 4; i++) { >> + g_assert_cmphex(page[i], ==, 0x0); >> + } >> + >> + spi_ctrl_start_user(); >> + writeb(AST2400_FLASH_BASE, WREN); >> + writeb(AST2400_FLASH_BASE, BULK_ERASE); >> + spi_ctrl_stop_user(); >> + >> + /* Recheck that some random page */ >> + read_page(some_page_addr, page); >> + for (i = 0; i < PAGE_SIZE / 4; i++) { >> + g_assert_cmphex(page[i], ==, 0xffffffff); >> + } >> +} >> + >> +static void test_write_page(void) >> +{ >> + uint32_t my_page_addr = 0x14000 * PAGE_SIZE; /* beyond 16MB */ >> + uint32_t some_page_addr = 0x15000 * PAGE_SIZE; >> + uint32_t page[PAGE_SIZE / 4]; >> + int i; >> + >> + spi_conf(CONF_ENABLE_W0); >> + >> + spi_ctrl_start_user(); >> + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); >> + writeb(AST2400_FLASH_BASE, PP); >> + writel(AST2400_FLASH_BASE, cpu_to_be32(my_page_addr)); >> + >> + /* Fill the page with its own addresses */ >> + for (i = 0; i < PAGE_SIZE / 4; i++) { >> + writel(AST2400_FLASH_BASE, cpu_to_be32(my_page_addr + i * 4)); >> + } >> + spi_ctrl_stop_user(); >> + >> + /* Check what was written */ >> + read_page(my_page_addr, page); >> + for (i = 0; i < PAGE_SIZE / 4; i++) { >> + g_assert_cmphex(page[i], ==, my_page_addr + i * 4); >> + } >> + >> + /* Check some other page. It should be full of 0xff */ >> + read_page(some_page_addr, page); >> + for (i = 0; i < PAGE_SIZE / 4; i++) { >> + g_assert_cmphex(page[i], ==, 0xffffffff); >> + } >> +} >> + >> +static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX"; >> + >> +int main(int argc, char **argv) >> +{ >> + int ret; >> + int fd; >> + char *args; >> + >> + g_test_init(&argc, &argv, NULL); >> + >> + fd = mkstemp(tmp_path); >> + g_assert(fd >= 0); >> + ret = ftruncate(fd, FLASH_SIZE); >> + g_assert(ret == 0); >> + close(fd); >> + >> + args = g_strdup_printf("-m 256 -machine palmetto-bmc " >> + "-drive file=%s,format=raw,if=mtd", >> + tmp_path); >> + qtest_start(args); >> + >> + qtest_add_func("/m25p80/read_jedec", test_read_jedec); >> + qtest_add_func("/m25p80/erase_sector", test_erase_sector); >> + qtest_add_func("/m25p80/erase_all", test_erase_all); >> + qtest_add_func("/m25p80/write_page", test_write_page); >> + >> + ret = g_test_run(); >> + >> + qtest_quit(global_qtest); >> + unlink(tmp_path); >> + g_free(args); >> + return ret; >> +} >
>>> +static void test_erase_sector(void) >>> +{ >>> + uint32_t some_page_addr = 0x600 * PAGE_SIZE; >>> + uint32_t page[PAGE_SIZE / 4]; >>> + int i; >>> + >>> + spi_conf(CONF_ENABLE_W0); >>> + >>> + spi_ctrl_start_user(); >>> + writeb(AST2400_FLASH_BASE, WREN); >>> + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); >>> + writeb(AST2400_FLASH_BASE, ERASE_SECTOR); >>> + writel(AST2400_FLASH_BASE, cpu_to_be32(some_page_addr)); >> Hi, >> >> I think you should not make any byte swapping because >> qtest for all write* instructions (see qtest.c:377). > > yes. on a BE, we should not byte swap. > > When on a LE host, the cpu_to_be32() call in the test byte-swaps > the address, tswap32() in qtest.c does nothing as the host endian > and guest endian are in sync and so the address reaches the > controller region in the expected order. > > When on a BE host, the cpu_to_be32() does nothing but tswap32() in > qtest.c reverses the order and so the address reaches the controller > region in the wrong order (LE). > > I see two possible fixes : > > 1 - replace the read* routines by out* (no tswap there) > 2 - add an extra byteswap on BE hosts using qtest_big_endian() as > in virtio-blk-test.c. see virtio_blk_fix_request() or : 3 - use memwrite/read which is I think the appropriate fix. Thanks, C.
On 4 July 2016 at 10:15, Cédric Le Goater <clg@kaod.org> wrote: > On 07/02/2016 08:05 PM, mar.krzeminski wrote: >> >> >> W dniu 28.06.2016 o 20:24, Cédric Le Goater pisze: >>> +static void test_erase_sector(void) >>> +{ >>> + uint32_t some_page_addr = 0x600 * PAGE_SIZE; >>> + uint32_t page[PAGE_SIZE / 4]; >>> + int i; >>> + >>> + spi_conf(CONF_ENABLE_W0); >>> + >>> + spi_ctrl_start_user(); >>> + writeb(AST2400_FLASH_BASE, WREN); >>> + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); >>> + writeb(AST2400_FLASH_BASE, ERASE_SECTOR); >>> + writel(AST2400_FLASH_BASE, cpu_to_be32(some_page_addr)); >> Hi, >> >> I think you should not make any byte swapping because >> qtest for all write* instructions (see qtest.c:377). > > yes. on a BE, we should not byte swap. > > When on a LE host, the cpu_to_be32() call in the test byte-swaps > the address, tswap32() in qtest.c does nothing as the host endian > and guest endian are in sync and so the address reaches the > controller region in the expected order. > > When on a BE host, the cpu_to_be32() does nothing but tswap32() in > qtest.c reverses the order and so the address reaches the controller > region in the wrong order (LE). > > I see two possible fixes : > > 1 - replace the read* routines by out* (no tswap there) This would be wrong: "out*" is a request for an I/O access, which is meaningless for ARM. (On x86 it's an actual outb/outw/outl instruction.) In any case it wouldn't change the number of byteswaps that happen: * "outl" qtest command calls cpu_outl(), which calls stl_p() on the value, to do "store in target endianness to buffer"; stl_p() will do a byteswap if the target and host endianness differ. The buffer is then passed to address_space_write(), which is a wrapper for address_space_rw(), which treats its buffer as a pile of bytes to be written. * "writel" qtest command does a tswap32s() on the data, which converts it to target endianness in a local variable. The address of the variable is then passed to cpu_physical_memory_write(), which is just a thin wrapper around address_space_rw(), which as above treats its buffer as a pile of bytes. So the two things end up the same, it's just that for writel we do the conversion from a host-ordered value to a target-ordered value in a direct tswapl(), but for outl this happens implicitly in cpu_outl()'s stl_p(). > 2 - add an extra byteswap on BE hosts using qtest_big_endian() as > in virtio-blk-test.c. see virtio_blk_fix_request() What is the test actually supposed to be doing? writel() says "write this 32 bit value as if the (guest) CPU wrote it to memory with a 32-bit write instruction". Your problem here is entirely on the test code side, I think. It should be issuing the same commands down the qtest protocol for any host endianness, but as it stands on a little endian host it will issue "writel 0x20000000 0x600" whereas on a big endian host it will issue "writel 0x20000000 0x60000". (virtio is special because it has some weird ideas about endianness due to being a virtual-only device with a spec written by all-the-world-is-little-endian x86 people, so it's a bad example to copy.) thanks -- PMM
On 07/04/2016 01:14 PM, Peter Maydell wrote: > On 4 July 2016 at 10:15, Cédric Le Goater <clg@kaod.org> wrote: >> On 07/02/2016 08:05 PM, mar.krzeminski wrote: >>> >>> >>> W dniu 28.06.2016 o 20:24, Cédric Le Goater pisze: > >>>> +static void test_erase_sector(void) >>>> +{ >>>> + uint32_t some_page_addr = 0x600 * PAGE_SIZE; >>>> + uint32_t page[PAGE_SIZE / 4]; >>>> + int i; >>>> + >>>> + spi_conf(CONF_ENABLE_W0); >>>> + >>>> + spi_ctrl_start_user(); >>>> + writeb(AST2400_FLASH_BASE, WREN); >>>> + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); >>>> + writeb(AST2400_FLASH_BASE, ERASE_SECTOR); >>>> + writel(AST2400_FLASH_BASE, cpu_to_be32(some_page_addr)); >>> Hi, >>> >>> I think you should not make any byte swapping because >>> qtest for all write* instructions (see qtest.c:377). >> >> yes. on a BE, we should not byte swap. >> >> When on a LE host, the cpu_to_be32() call in the test byte-swaps >> the address, tswap32() in qtest.c does nothing as the host endian >> and guest endian are in sync and so the address reaches the >> controller region in the expected order. >> >> When on a BE host, the cpu_to_be32() does nothing but tswap32() in >> qtest.c reverses the order and so the address reaches the controller >> region in the wrong order (LE). >> >> I see two possible fixes : >> >> 1 - replace the read* routines by out* (no tswap there) > > This would be wrong: "out*" is a request for an I/O access, yes. that felt really wrong. > which is meaningless for ARM. (On x86 it's an actual outb/outw/outl > instruction.) In any case it wouldn't change the number of > byteswaps that happen: > > * "outl" qtest command calls cpu_outl(), which calls > stl_p() on the value, to do "store in target endianness > to buffer"; stl_p() will do a byteswap if the target and > host endianness differ. The buffer is then passed to > address_space_write(), which is a wrapper for > address_space_rw(), which treats its buffer as a pile > of bytes to be written. > * "writel" qtest command does a tswap32s() on the data, which > converts it to target endianness in a local variable. > The address of the variable is then passed to > cpu_physical_memory_write(), which is just a thin wrapper > around address_space_rw(), which as above treats its > buffer as a pile of bytes. > > So the two things end up the same, it's just that for writel > we do the conversion from a host-ordered value to a > target-ordered value in a direct tswapl(), but for outl > this happens implicitly in cpu_outl()'s stl_p(). ok. thanks for the summary/explanation. >> 2 - add an extra byteswap on BE hosts using qtest_big_endian() as >> in virtio-blk-test.c. see virtio_blk_fix_request() > > What is the test actually supposed to be doing? > writel() says "write this 32 bit value as if the (guest) CPU > wrote it to memory with a 32-bit write instruction". The test (and the guest) is writing and reading data on the memory region used by the SPI controller. This 'data' is then passed on to the SPI flash module objects which expects BE order when there are flash storage addresses are in the flow. So I think the test needs to use mem{write,read} and not write*. The result looks correct in the code. I will send a patchset right after starting with this patch. > Your problem here is entirely on the test code side, I think. As the guest boots correctly, I would say yes also. > It should be issuing the same commands down the qtest protocol > for any host endianness, but as it stands on a little endian > host it will issue "writel 0x20000000 0x600" whereas on a big > endian host it will issue "writel 0x20000000 0x60000". > > (virtio is special because it has some weird ideas about > endianness due to being a virtual-only device with a spec > written by all-the-world-is-little-endian x86 people, so > it's a bad example to copy.) yes, we had a taste of that when virtio support was added for the ppc64be guests :) Thanks, C.
On 4 July 2016 at 13:01, Cédric Le Goater <clg@kaod.org> wrote: > On 07/04/2016 01:14 PM, Peter Maydell wrote: >> What is the test actually supposed to be doing? >> writel() says "write this 32 bit value as if the (guest) CPU >> wrote it to memory with a 32-bit write instruction". > > The test (and the guest) is writing and reading data on the memory > region used by the SPI controller. This 'data' is then passed on > to the SPI flash module objects which expects BE order when there > are flash storage addresses are in the flow. > > So I think the test needs to use mem{write,read} and not write*. > The result looks correct in the code. I will send a patchset > right after starting with this patch. If you were writing this test in a bit of native ARM code running in the guest, how would you write it? memread/memwrite are only the correct answer if you'd write the native arm code as something like memcpy(SPI_REGISTER, buf, len), which is not generally the way you talk to devices. thanks -- PMM
On 07/04/2016 02:11 PM, Peter Maydell wrote: > On 4 July 2016 at 13:01, Cédric Le Goater <clg@kaod.org> wrote: >> On 07/04/2016 01:14 PM, Peter Maydell wrote: >>> What is the test actually supposed to be doing? >>> writel() says "write this 32 bit value as if the (guest) CPU >>> wrote it to memory with a 32-bit write instruction". >> >> The test (and the guest) is writing and reading data on the memory >> region used by the SPI controller. This 'data' is then passed on >> to the SPI flash module objects which expects BE order when there >> are flash storage addresses are in the flow. >> >> So I think the test needs to use mem{write,read} and not write*. >> The result looks correct in the code. I will send a patchset >> right after starting with this patch. > > If you were writing this test in a bit of native ARM code > running in the guest, how would you write it? > memread/memwrite are only the correct answer if you'd write > the native arm code as something like > memcpy(SPI_REGISTER, buf, len), which is not generally the > way you talk to devices. The SMC/SPI controller are driven by mmios and the flash module in a very similar way. The modules are mapped at some address, 0x2000000 for the BMC, 0x3000000 for the host firmware. Writing to the mapped address triggers SPI transfers, you need to put the slave in user mode for that, by setting the appropriate registers in the controller. When not in that mode, you are in command mode, and in this case you access directly the contents of the flash. Thanks, C.
diff --git a/tests/Makefile.include b/tests/Makefile.include index 6c09962f7581..149f92585c1b 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -252,6 +252,7 @@ gcov-files-sparc-y += hw/timer/m48t59.c gcov-files-sparc64-y += hw/timer/m48t59.c check-qtest-arm-y = tests/tmp105-test$(EXESUF) check-qtest-arm-y += tests/ds1338-test$(EXESUF) +check-qtest-arm-y += tests/m25p80-test$(EXESUF) gcov-files-arm-y += hw/misc/tmp105.c check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) gcov-files-arm-y += arm-softmmu/hw/block/virtio-blk.c @@ -568,6 +569,7 @@ tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \ tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y) tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/m25p80-test$(EXESUF): tests/m25p80-test.o tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y) diff --git a/tests/m25p80-test.c b/tests/m25p80-test.c new file mode 100644 index 000000000000..305c52319a33 --- /dev/null +++ b/tests/m25p80-test.c @@ -0,0 +1,242 @@ +/* + * QTest testcase for the M25P80 Flash (Using the AST2400 SPI Controller) + * + * Copyright (C) 2016 IBM Corp. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/bswap.h" +#include "libqtest.h" + +/* + * AST2400 SPI Controller registers + */ +#define R_CONF 0x00 +#define CONF_ENABLE_W0 (1 << 16) +#define R_CE_CTRL 0x04 +#define CRTL_EXTENDED0 0 /* 32 bit addressing for SPI */ +#define R_CTRL0 0x10 +#define CTRL_CE_STOP_ACTIVE (1 << 2) +#define CTRL_USERMODE 0x3 + +#define AST2400_FMC_BASE 0x1E620000 +#define AST2400_FLASH_BASE 0x20000000 + +/* + * Flash commands + */ +enum { + JEDEC_READ = 0x9f, + BULK_ERASE = 0xc7, + READ = 0x03, + PP = 0x02, + WREN = 0x6, + EN_4BYTE_ADDR = 0xB7, + ERASE_SECTOR = 0xd8, +}; + +#define FLASH_JEDEC 0x20ba19 /* n25q256a */ +#define FLASH_SIZE (32 * 1024 * 1024) + +#define PAGE_SIZE 256 + +static void spi_conf(uint32_t value) +{ + uint32_t conf = readl(AST2400_FMC_BASE + R_CONF); + + conf |= value; + writel(AST2400_FMC_BASE + R_CONF, conf); +} + +static void spi_ctrl_start_user(void) +{ + uint32_t ctrl = readl(AST2400_FMC_BASE + R_CTRL0); + + ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; + writel(AST2400_FMC_BASE + R_CTRL0, ctrl); + + ctrl &= ~CTRL_CE_STOP_ACTIVE; + writel(AST2400_FMC_BASE + R_CTRL0, ctrl); +} + +static void spi_ctrl_stop_user(void) +{ + uint32_t ctrl = readl(AST2400_FMC_BASE + R_CTRL0); + + ctrl |= CTRL_USERMODE | CTRL_CE_STOP_ACTIVE; + writel(AST2400_FMC_BASE + R_CTRL0, ctrl); +} + +static void test_read_jedec(void) +{ + uint32_t jedec = 0x0; + + spi_conf(CONF_ENABLE_W0); + + spi_ctrl_start_user(); + writeb(AST2400_FLASH_BASE, JEDEC_READ); + jedec |= readb(AST2400_FLASH_BASE) << 16; + jedec |= readb(AST2400_FLASH_BASE) << 8; + jedec |= readb(AST2400_FLASH_BASE); + spi_ctrl_stop_user(); + + g_assert_cmphex(jedec, ==, FLASH_JEDEC); +} + +static void read_page(uint32_t addr, uint32_t *page) +{ + int i; + + spi_ctrl_start_user(); + + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); + writeb(AST2400_FLASH_BASE, READ); + writel(AST2400_FLASH_BASE, cpu_to_be32(addr)); + + /* Continuous read are supported */ + for (i = 0; i < PAGE_SIZE / 4; i++) { + page[i] = be32_to_cpu(readl(AST2400_FLASH_BASE)); + } + spi_ctrl_stop_user(); +} + +static void test_erase_sector(void) +{ + uint32_t some_page_addr = 0x600 * PAGE_SIZE; + uint32_t page[PAGE_SIZE / 4]; + int i; + + spi_conf(CONF_ENABLE_W0); + + spi_ctrl_start_user(); + writeb(AST2400_FLASH_BASE, WREN); + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); + writeb(AST2400_FLASH_BASE, ERASE_SECTOR); + writel(AST2400_FLASH_BASE, cpu_to_be32(some_page_addr)); + spi_ctrl_stop_user(); + + /* Previous page should be full of zeroes as backend is not + * initialized */ + read_page(some_page_addr - PAGE_SIZE, page); + for (i = 0; i < PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], ==, 0x0); + } + + /* But this one was erased */ + read_page(some_page_addr, page); + for (i = 0; i < PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], ==, 0xffffffff); + } +} + +static void test_erase_all(void) +{ + uint32_t some_page_addr = 0x15000 * PAGE_SIZE; + uint32_t page[PAGE_SIZE / 4]; + int i; + + spi_conf(CONF_ENABLE_W0); + + /* Check some random page. Should be full of zeroes as backend is + * not initialized */ + read_page(some_page_addr, page); + for (i = 0; i < PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], ==, 0x0); + } + + spi_ctrl_start_user(); + writeb(AST2400_FLASH_BASE, WREN); + writeb(AST2400_FLASH_BASE, BULK_ERASE); + spi_ctrl_stop_user(); + + /* Recheck that some random page */ + read_page(some_page_addr, page); + for (i = 0; i < PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], ==, 0xffffffff); + } +} + +static void test_write_page(void) +{ + uint32_t my_page_addr = 0x14000 * PAGE_SIZE; /* beyond 16MB */ + uint32_t some_page_addr = 0x15000 * PAGE_SIZE; + uint32_t page[PAGE_SIZE / 4]; + int i; + + spi_conf(CONF_ENABLE_W0); + + spi_ctrl_start_user(); + writeb(AST2400_FLASH_BASE, EN_4BYTE_ADDR); + writeb(AST2400_FLASH_BASE, PP); + writel(AST2400_FLASH_BASE, cpu_to_be32(my_page_addr)); + + /* Fill the page with its own addresses */ + for (i = 0; i < PAGE_SIZE / 4; i++) { + writel(AST2400_FLASH_BASE, cpu_to_be32(my_page_addr + i * 4)); + } + spi_ctrl_stop_user(); + + /* Check what was written */ + read_page(my_page_addr, page); + for (i = 0; i < PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], ==, my_page_addr + i * 4); + } + + /* Check some other page. It should be full of 0xff */ + read_page(some_page_addr, page); + for (i = 0; i < PAGE_SIZE / 4; i++) { + g_assert_cmphex(page[i], ==, 0xffffffff); + } +} + +static char tmp_path[] = "/tmp/qtest.m25p80.XXXXXX"; + +int main(int argc, char **argv) +{ + int ret; + int fd; + char *args; + + g_test_init(&argc, &argv, NULL); + + fd = mkstemp(tmp_path); + g_assert(fd >= 0); + ret = ftruncate(fd, FLASH_SIZE); + g_assert(ret == 0); + close(fd); + + args = g_strdup_printf("-m 256 -machine palmetto-bmc " + "-drive file=%s,format=raw,if=mtd", + tmp_path); + qtest_start(args); + + qtest_add_func("/m25p80/read_jedec", test_read_jedec); + qtest_add_func("/m25p80/erase_sector", test_erase_sector); + qtest_add_func("/m25p80/erase_all", test_erase_all); + qtest_add_func("/m25p80/write_page", test_write_page); + + ret = g_test_run(); + + qtest_quit(global_qtest); + unlink(tmp_path); + g_free(args); + return ret; +}