@@ -190,8 +190,7 @@ static void pc_q35_init(MachineState *machine)
PC_MACHINE_ACPI_DEVICE_PROP, &error_abort);
ich9_lpc = ICH9_LPC_DEVICE(lpc);
- ich9_lpc->pic = gsi;
- ich9_lpc->ioapic = gsi_state->ioapic_irq;
+ ich9_lpc->gsi = gsi;
pci_bus_irqs(host_bus, ich9_lpc_set_irq, ich9_lpc_map_irq, ich9_lpc,
ICH9_LPC_NB_PIRQS);
pci_bus_set_route_irq_fn(host_bus, ich9_route_intx_pin_to_irq);
@@ -225,7 +225,7 @@ static void ich9_lpc_update_pic(ICH9LPCState *lpc, int gsi)
pic_level |= lpc->sci_level;
}
- qemu_set_irq(lpc->pic[gsi], pic_level);
+ qemu_set_irq(lpc->gsi[gsi], pic_level);
}
/* APIC mode: GSIx: PIRQ[A-H] -> GSI 16, ... no pirq shares same APIC pins. */
@@ -251,7 +251,7 @@ static void ich9_lpc_update_apic(ICH9LPCState *lpc, int gsi)
level |= lpc->sci_level;
}
- qemu_set_irq(lpc->ioapic[gsi], level);
+ qemu_set_irq(lpc->gsi[gsi], level);
}
void ich9_lpc_set_irq(void *opaque, int pirq, int level)
@@ -68,8 +68,7 @@ typedef struct ICH9LPCState {
MemoryRegion rcrb_mem; /* root complex register block */
Notifier machine_ready;
- qemu_irq *pic;
- qemu_irq *ioapic;
+ qemu_irq *gsi;
} ICH9LPCState;
Object *ich9_lpc_find(void);