| Message ID | 20160627090248.23621-4-josephl@nvidia.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
On 06/27/2016 03:02 AM, Joseph Lo wrote: > The BPMP is a specific processor in Tegra chip, which is designed for > booting process handling and offloading the power management tasks > from the CPU. The binding document defines the resources that would be > used by the BPMP firmware driver, which can create the interprocessor > communication (IPC) between the CPU and BPMP. > diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt > +The BPMP is a specific processor in Tegra chip, which is designed for > +booting process handling and offloading the power management tasks from > +the CPU. The binding document defines the resources that would be used by > +the BPMP firmware driver, which can create the interprocessor > +communication (IPC) between the CPU and BPMP. s/power management/power management, clock management, and reset control/? > +Required properties: > +- name : Should be bpmp > +- compatible : Should be "nvidia,tegra<chip>-bpmp" Again, I'd suggest wording this as: - compatible Array of strings. One of: - "nvidia,tegra186-bpmp" > +- mboxes : The phandle of mailbox controller and the channel ID s/channel ID/mailbox specifier/. > + See "Documentation/devicetree/bindings/mailbox/ > + nvidia,tegra186-hsp.txt" and "Documentation/devicetree/ > + bindings/mailbox/mailbox.txt" for more details about the generic > + mailbox controller and mailbox client driver bindings. I'd rather not split the filenames across lines, since that makes grep fail to match. Perhaps add the following text to the introductory section at the start of the file to avoid having to mention some of the filenames in an indented block of text: ========== This node is a mailbox consumer. See the following file for details of the mailbox subsystem, and the specifiers implemented by the relevant provider(s): - Documentation/devicetree/bindings/mailbox/mailbox.txt - Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt This node is a clock and reset provider. See the following files for general documentation of those features, and the specifiers implemented by this node: - Documentation/devicetree/bindings/clock/clock-bindings.txt - include/dt-bindings/clock/tegra186-clock.h - Documentation/devicetree/bindings/reset/reset.txt - include/dt-bindings/reset/tegra186-reset.h ========== Related, I would expect those two header files (tegra186-clock.h and tegra186-reset.h) to be part of this patch, since they form part of the definition of this binding. > +The shared memory bindings for BPMP > +----------------------------------- > + > +The shared memory area for the IPC TX and RX between CPU and BPMP are > +predefined and work on top of sysram, which is a sram inside the chip. s/a sram/an SRAM/. > +Example: ... > +bpmp@d0000000 { There should be no unit address ("@d0000000") in the node name, since there's no reg property. -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
On 06/28/2016 12:08 AM, Stephen Warren wrote: > On 06/27/2016 03:02 AM, Joseph Lo wrote: >> The BPMP is a specific processor in Tegra chip, which is designed for >> booting process handling and offloading the power management tasks >> from the CPU. The binding document defines the resources that would be >> used by the BPMP firmware driver, which can create the interprocessor >> communication (IPC) between the CPU and BPMP. > >> diff --git >> a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt >> b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt > >> +The BPMP is a specific processor in Tegra chip, which is designed for >> +booting process handling and offloading the power management tasks from >> +the CPU. The binding document defines the resources that would be >> used by >> +the BPMP firmware driver, which can create the interprocessor >> +communication (IPC) between the CPU and BPMP. > > s/power management/power management, clock management, and reset control/? Yes. > >> +Required properties: >> +- name : Should be bpmp >> +- compatible : Should be "nvidia,tegra<chip>-bpmp" > > Again, I'd suggest wording this as: > > - compatible > Array of strings. > One of: > - "nvidia,tegra186-bpmp" Okay. > >> +- mboxes : The phandle of mailbox controller and the channel ID > > s/channel ID/mailbox specifier/. > >> + See "Documentation/devicetree/bindings/mailbox/ >> + nvidia,tegra186-hsp.txt" and "Documentation/devicetree/ >> + bindings/mailbox/mailbox.txt" for more details about the generic >> + mailbox controller and mailbox client driver bindings. > > I'd rather not split the filenames across lines, since that makes grep > fail to match. Perhaps add the following text to the introductory > section at the start of the file to avoid having to mention some of the > filenames in an indented block of text: Thanks. > > ========== > This node is a mailbox consumer. See the following file for details of > the mailbox subsystem, and the specifiers implemented by the relevant > provider(s): > > - Documentation/devicetree/bindings/mailbox/mailbox.txt > - Documentation/devicetree/bindings/mailbox/nvidia,tegra186-hsp.txt > > This node is a clock and reset provider. See the following files for > general documentation of those features, and the specifiers implemented > by this node: > > - Documentation/devicetree/bindings/clock/clock-bindings.txt > - include/dt-bindings/clock/tegra186-clock.h > - Documentation/devicetree/bindings/reset/reset.txt > - include/dt-bindings/reset/tegra186-reset.h > ========== > > Related, I would expect those two header files (tegra186-clock.h and > tegra186-reset.h) to be part of this patch, since they form part of the > definition of this binding. Okay. Will add them. > >> +The shared memory bindings for BPMP >> +----------------------------------- >> + >> +The shared memory area for the IPC TX and RX between CPU and BPMP are >> +predefined and work on top of sysram, which is a sram inside the chip. > > s/a sram/an SRAM/. > >> +Example: > ... >> +bpmp@d0000000 { > > There should be no unit address ("@d0000000") in the node name, since > there's no reg property. Thanks, -Joseph -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html
diff --git a/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt new file mode 100644 index 000000000000..34a252d87e17 --- /dev/null +++ b/Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt @@ -0,0 +1,61 @@ +NVIDIA Tegra Boot and Power Management Processor (BPMP) + +The BPMP is a specific processor in Tegra chip, which is designed for +booting process handling and offloading the power management tasks from +the CPU. The binding document defines the resources that would be used by +the BPMP firmware driver, which can create the interprocessor +communication (IPC) between the CPU and BPMP. + +Required properties: +- name : Should be bpmp +- compatible : Should be "nvidia,tegra<chip>-bpmp" +- mboxes : The phandle of mailbox controller and the channel ID + See "Documentation/devicetree/bindings/mailbox/ + nvidia,tegra186-hsp.txt" and "Documentation/devicetree/ + bindings/mailbox/mailbox.txt" for more details about the generic + mailbox controller and mailbox client driver bindings. +- shmem : List of the phandle of the TX and RX shared memory area that + the IPC between CPU and BPMP is based on. +- #clock-cells : Should be 1. +- #reset-cells : Should be 1. + +The shared memory bindings for BPMP +----------------------------------- + +The shared memory area for the IPC TX and RX between CPU and BPMP are +predefined and work on top of sysram, which is a sram inside the chip. + +See "Documentation/devicetree/bindings/sram/sram.txt" for the bindings. + +Example: + +hsp_top: hsp@03c00000 { + ... + #mbox-cells = <1>; +}; + +bpmp@d0000000 { + compatible = "nvidia,tegra186-bpmp"; + mboxes = <&hsp_mbox HSP_DB_MASTER_BPMP>; + shmem = <&cpu_bpmp_tx &cpu_bpmp_rx>; + #clock-cells = <1>; + #reset-cells = <1>; +}; + +sysram@30000000 { + compatible = "nvidia,tegra186-sysram", "mmio-ram"; + reg = <0x0 0x30000000 0x0 0x50000>; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0 0x0 0x0 0x30000000 0x0 0x50000>; + + cpu_bpmp_tx: bpmp_shmem@4e000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4e000 0x0 0x1000>; + }; + + cpu_bpmp_rx: bpmp_shmem@4f000 { + compatible = "nvidia,tegra186-bpmp-shmem"; + reg = <0x0 0x4f000 0x0 0x1000>; + }; +};
The BPMP is a specific processor in Tegra chip, which is designed for booting process handling and offloading the power management tasks from the CPU. The binding document defines the resources that would be used by the BPMP firmware driver, which can create the interprocessor communication (IPC) between the CPU and BPMP. Signed-off-by: Joseph Lo <josephl@nvidia.com> --- .../bindings/firmware/nvidia,tegra186-bpmp.txt | 61 ++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 Documentation/devicetree/bindings/firmware/nvidia,tegra186-bpmp.txt