| Message ID | 20160623105231.24383-1-thierry.reding@gmail.com |
|---|---|
| State | Accepted |
| Headers | show |
On 23/06/16 11:52, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > It turns out that sor_safe, rather than pll_p, is the parent of the > dpaux and dpaux1 clocks. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/clk/tegra/clk-tegra210.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c > index aab32af77aa2..fe295b4102ca 100644 > --- a/drivers/clk/tegra/clk-tegra210.c > +++ b/drivers/clk/tegra/clk-tegra210.c > @@ -2466,11 +2466,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, > 1, 2); > clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; > > - clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, > + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, > 1, 17, 181); > clks[TEGRA210_CLK_DPAUX] = clk; > > - clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base, > + clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, > 1, 17, 207); > clks[TEGRA210_CLK_DPAUX1] = clk; Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Cheers Jon
On 6/23/2016 6:52 AM, Thierry Reding wrote: > From: Thierry Reding <treding@nvidia.com> > > It turns out that sor_safe, rather than pll_p, is the parent of the > dpaux and dpaux1 clocks. > > Signed-off-by: Thierry Reding <treding@nvidia.com> > --- > drivers/clk/tegra/clk-tegra210.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c > index aab32af77aa2..fe295b4102ca 100644 > --- a/drivers/clk/tegra/clk-tegra210.c > +++ b/drivers/clk/tegra/clk-tegra210.c > @@ -2466,11 +2466,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, > 1, 2); > clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; > > - clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, > + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, > 1, 17, 181); > clks[TEGRA210_CLK_DPAUX] = clk; > > - clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base, > + clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, > 1, 17, 207); > clks[TEGRA210_CLK_DPAUX1] = clk; > > Acked-by: Rhyland Klein <rklein@nvidia.com>
diff --git a/drivers/clk/tegra/clk-tegra210.c b/drivers/clk/tegra/clk-tegra210.c index aab32af77aa2..fe295b4102ca 100644 --- a/drivers/clk/tegra/clk-tegra210.c +++ b/drivers/clk/tegra/clk-tegra210.c @@ -2466,11 +2466,11 @@ static __init void tegra210_periph_clk_init(void __iomem *clk_base, 1, 2); clks[TEGRA210_CLK_XUSB_SS_DIV2] = clk; - clk = tegra_clk_register_periph_fixed("dpaux", "pll_p", 0, clk_base, + clk = tegra_clk_register_periph_fixed("dpaux", "sor_safe", 0, clk_base, 1, 17, 181); clks[TEGRA210_CLK_DPAUX] = clk; - clk = tegra_clk_register_periph_fixed("dpaux1", "pll_p", 0, clk_base, + clk = tegra_clk_register_periph_fixed("dpaux1", "sor_safe", 0, clk_base, 1, 17, 207); clks[TEGRA210_CLK_DPAUX1] = clk;