Patchwork [mips] Enable loongson vector shift instructions

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Submitter Mingjie Xing
Date Sept. 6, 2010, 8:12 a.m.
Message ID <AANLkTiknZGxEaCp0S+1VsGawEBH158i7V4SZ6v_f7R-c@mail.gmail.com>
Download mbox | patch
Permalink /patch/63893/
State New
Headers show

Comments

Mingjie Xing - Sept. 6, 2010, 8:12 a.m.
Hello,

This patch enables the loongson vector shift instructions to be
generated by auto-vectorization.  Is this OK?

Thanks,
Mingjie

ChangeLog

        * config/mips/loongson.md (loongson_psll<V_suffix>): Rename to...
        (ashl<mode>3): ...this.
        (loongson_psra<V_suffix>): Rename to...
        (ashr<mode>3): ...this.
        (loongson_psrl<V_suffix>): Rename to...
        (lshr<mode>3): ...this.
        * config/mips/mips.c (CODE_FOR_loongson_psllh): Define.
        (CODE_FOR_loongson_psllw): Define.
        (CODE_FOR_loongson_psrlh): Define.
        (CODE_FOR_loongson_psrlw): Define.
        (CODE_FOR_loongson_psrah): Define.
        (CODE_FOR_loongson_psraw): Define.
Richard Sandiford - Sept. 7, 2010, 6:13 p.m.
Mingjie Xing <mingjie.xing@gmail.com> writes:
>         * config/mips/loongson.md (loongson_psll<V_suffix>): Rename to...
>         (ashl<mode>3): ...this.
>         (loongson_psra<V_suffix>): Rename to...
>         (ashr<mode>3): ...this.
>         (loongson_psrl<V_suffix>): Rename to...
>         (lshr<mode>3): ...this.
>         * config/mips/mips.c (CODE_FOR_loongson_psllh): Define.
>         (CODE_FOR_loongson_psllw): Define.
>         (CODE_FOR_loongson_psrlh): Define.
>         (CODE_FOR_loongson_psrlw): Define.
>         (CODE_FOR_loongson_psrah): Define.
>         (CODE_FOR_loongson_psraw): Define.

OK, thanks.

Richard

Patch

Index: config/mips/loongson.md
===================================================================
--- config/mips/loongson.md	(revision 163892)
+++ config/mips/loongson.md	(working copy)
@@ -411,7 +411,7 @@ 
   [(set_attr "type" "fmul")])
 
 ;; Shift left logical.
-(define_insn "loongson_psll<V_suffix>"
+(define_insn "ashl<mode>3"
   [(set (match_operand:VWH 0 "register_operand" "=f")
         (ashift:VWH (match_operand:VWH 1 "register_operand" "f")
 		    (match_operand:SI 2 "register_operand" "f")))]
@@ -420,7 +420,7 @@ 
   [(set_attr "type" "fmul")])
 
 ;; Shift right arithmetic.
-(define_insn "loongson_psra<V_suffix>"
+(define_insn "ashr<mode>3"
   [(set (match_operand:VWH 0 "register_operand" "=f")
         (ashiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
 		      (match_operand:SI 2 "register_operand" "f")))]
@@ -429,7 +429,7 @@ 
   [(set_attr "type" "fdiv")])
 
 ;; Shift right logical.
-(define_insn "loongson_psrl<V_suffix>"
+(define_insn "lshr<mode>3"
   [(set (match_operand:VWH 0 "register_operand" "=f")
         (lshiftrt:VWH (match_operand:VWH 1 "register_operand" "f")
 		      (match_operand:SI 2 "register_operand" "f")))]
Index: config/mips/mips.c
===================================================================
--- config/mips/mips.c	(revision 163892)
+++ config/mips/mips.c	(working copy)
@@ -12714,6 +12714,12 @@  AVAIL_NON_MIPS16 (cache, TARGET_CACHE_BU
 #define CODE_FOR_loongson_pmulhuh CODE_FOR_umulv4hi3_highpart
 #define CODE_FOR_loongson_pmulhh CODE_FOR_smulv4hi3_highpart
 #define CODE_FOR_loongson_pmullh CODE_FOR_mulv4hi3
+#define CODE_FOR_loongson_psllh CODE_FOR_ashlv4hi3
+#define CODE_FOR_loongson_psllw CODE_FOR_ashlv2si3
+#define CODE_FOR_loongson_psrlh CODE_FOR_lshrv4hi3
+#define CODE_FOR_loongson_psrlw CODE_FOR_lshrv2si3
+#define CODE_FOR_loongson_psrah CODE_FOR_ashrv4hi3
+#define CODE_FOR_loongson_psraw CODE_FOR_ashrv2si3
 #define CODE_FOR_loongson_psubw CODE_FOR_subv2si3
 #define CODE_FOR_loongson_psubh CODE_FOR_subv4hi3
 #define CODE_FOR_loongson_psubb CODE_FOR_subv8qi3