From patchwork Mon Sep 6 07:46:26 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 63889 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id 52DCDB70E0 for ; Mon, 6 Sep 2010 17:56:52 +1000 (EST) Received: from localhost ([127.0.0.1]:44233 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OsWYS-0003j2-Pu for incoming@patchwork.ozlabs.org; Mon, 06 Sep 2010 03:55:52 -0400 Received: from [140.186.70.92] (port=38030 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OsWCa-0000TF-K3 for qemu-devel@nongnu.org; Mon, 06 Sep 2010 03:33:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OsWCO-0005nc-13 for qemu-devel@nongnu.org; Mon, 06 Sep 2010 03:33:12 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:42962) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OsWCN-0005mT-8O for qemu-devel@nongnu.org; Mon, 06 Sep 2010 03:33:03 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id B2F40107AA3; Mon, 6 Sep 2010 16:32:58 +0900 (JST) Received: (nullmailer pid 21931 invoked by uid 1000); Mon, 06 Sep 2010 07:46:28 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Mon, 6 Sep 2010 16:46:26 +0900 Message-Id: X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, etmartin@cisco.com, wexu2@cisco.com, mst@redhat.com, adhyas@gmail.com, yamahata@valinux.co.jp Subject: [Qemu-devel] [PATCH 12/14] pcie downstream port: pci express switch downstream port. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org pcie switch downstream port. Signed-off-by: Isaku Yamahata --- Makefile.objs | 1 + hw/pcie_downstream.c | 224 ++++++++++++++++++++++++++++++++++++++++++++++++++ hw/pcie_downstream.h | 33 ++++++++ 3 files changed, 258 insertions(+), 0 deletions(-) create mode 100644 hw/pcie_downstream.c create mode 100644 hw/pcie_downstream.h diff --git a/Makefile.objs b/Makefile.objs index e7a08dc..6904b02 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -140,6 +140,7 @@ hw-obj-y = hw-obj-y += vl.o loader.o hw-obj-y += virtio.o virtio-console.o hw-obj-y += fw_cfg.o pci.o pci_host.o pcie_host.o pci_bridge.o pcie_upstream.o +hw-obj-y += pcie_downstream.o hw-obj-y += watchdog.o hw-obj-$(CONFIG_ISA_MMIO) += isa_mmio.o hw-obj-$(CONFIG_ECC) += ecc.o diff --git a/hw/pcie_downstream.c b/hw/pcie_downstream.c new file mode 100644 index 0000000..a04efc9 --- /dev/null +++ b/hw/pcie_downstream.c @@ -0,0 +1,224 @@ +/* + * pcie_downstream.c + * + * Copyright (c) 2010 Isaku Yamahata + * VA Linux Systems Japan K.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "pci_ids.h" +#include "msi.h" +#include "pcie.h" +#include "pcie_downstream.h" + +/* For now, TI XIO3130 is borrowed. need to get its own id? */ +#define PCI_DEVICE_ID_TI_XIO3130D 0x8233 /* downstream port */ +#define XIO3130_REVISION 0x1 +#define XIO3130_MSI_OFFSET 0x70 +#define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT +#define XIO3130_MSI_NR_VECTOR 1 +#define XIO3130_SSVID_OFFSET 0x80 +#define XIO3130_SSVID_SVID 0 +#define XIO3130_SSVID_SSID 0 +#define XIO3130_EXP_OFFSET 0x90 +#define XIO3130_AER_OFFSET 0x100 + +#define PCIE_DOWNSTREAM_VID PCI_VENDOR_ID_TI +#define PCIE_DOWNSTREAM_DID PCI_DEVICE_ID_TI_XIO3130D +#define PCIE_DOWNSTREAM_REVISION XIO3130_REVISION +#define PCIE_DOWNSTREAM_MSI_SUPPORTED_FLAGS XIO3130_MSI_SUPPORTED_FLAGS +#define PCIE_DOWNSTREAM_MSI_NR_VECTOR XIO3130_MSI_NR_VECTOR +#define PCIE_DOWNSTREAM_MSI_OFFSET XIO3130_MSI_OFFSET +#define PCIE_DOWNSTREAM_SSVID_OFFSET XIO3130_SSVID_OFFSET +#define PCIE_DOWNSTREAM_SVID XIO3130_SSVID_SVID +#define PCIE_DOWNSTREAM_SSID XIO3130_SSVID_SSID +#define PCIE_DOWNSTREAM_EXP_OFFSET XIO3130_EXP_OFFSET +#define PCIE_DOWNSTREAM_AER_OFFSET XIO3130_AER_OFFSET + +static void pcie_downstream_write_config(PCIDevice *d, uint32_t address, + uint32_t val, int len) +{ + uint16_t sltctl = + pci_get_word(d->config + pci_pcie_cap(d) + PCI_EXP_SLTCTL); + pci_bridge_write_config(d, address, val, len); + pcie_cap_flr_write_config(d, address, val, len); + pcie_cap_deverr_write_config(d, address, val, len); + pcie_cap_slot_write_config(d, address, val, len, sltctl); + msi_write_config(d, address, val, len); + pcie_aer_write_config_vbridge(d, address, val, len); + pcie_aer_write_config(d, address, val, len); +} + +static void pcie_downstream_reset(DeviceState *qdev) +{ + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); + msi_reset(d); + pcie_cap_deverr_reset(d); + pcie_cap_slot_reset(d); + pcie_cap_ari_reset(d); + pci_bridge_reset(qdev); +} + +static void pcie_downstream_flr(PCIDevice *d) +{ + /* TODO: not enabled until qdev reset clean up + waiting for Anthony's qdev cealn up */ +#if 0 + /* So far, sticky bit registers or register which must be preserved + over FLR aren't emulated. So just reset this device. */ + pci_device_reset(d); +#endif +} + +static int pcie_downstream_initfn(PCIDevice *d) +{ + PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); + PCIEPort *p = DO_UPCAST(PCIEPort, br, br); + PCIESlot *s = DO_UPCAST(PCIESlot, port, p); + int rc; + + rc = pci_bridge_initfn(d); + if (rc < 0) { + return rc; + } + + pcie_port_init_reg(d); + pci_config_set_vendor_id(d->config, PCIE_DOWNSTREAM_VID); + pci_config_set_device_id(d->config, PCIE_DOWNSTREAM_DID); + d->config[PCI_REVISION_ID] = PCIE_DOWNSTREAM_REVISION; + + rc = msi_init(d, PCIE_DOWNSTREAM_MSI_OFFSET, PCIE_DOWNSTREAM_MSI_NR_VECTOR, + PCIE_DOWNSTREAM_MSI_SUPPORTED_FLAGS); + if (rc < 0) { + return rc; + } + rc = pci_bridge_ssvid_init(d, PCIE_DOWNSTREAM_SSVID_OFFSET, + PCIE_DOWNSTREAM_SVID, PCIE_DOWNSTREAM_SSID); + if (rc < 0) { + return rc; + } + rc = pci_pcie_cap_init(d, PCIE_DOWNSTREAM_EXP_OFFSET, + PCI_EXP_TYPE_DOWNSTREAM, p->port); + if (rc < 0) { + return rc; + } + pcie_cap_flr_init(d, &pcie_downstream_flr); + pcie_cap_deverr_init(d); + pcie_cap_slot_init(d, s->slot); + pcie_chassis_create(s->chassis); + rc = pcie_chassis_add_slot(s); + if (rc < 0) { + return rc; + } + pcie_cap_ari_init(d); + rc = pcie_aer_init(d, PCIE_DOWNSTREAM_AER_OFFSET); + if (rc < 0) { + return rc; + } + + return 0; +} + +static int pcie_downstream_exitfn(PCIDevice *d) +{ + int rc; + + pcie_aer_exit(d); + msi_uninit(d); + rc = pci_pcie_cap_exit(d); + if (rc < 0) { + return rc; + } + return pci_bridge_exitfn(d); +} + +PCIESlot *pcie_downstream_init(PCIBus *bus, + int devfn, bool multifunction, + const char *bus_name, pci_map_irq_fn map_irq, + uint8_t port, uint8_t chassis, uint16_t slot) +{ + PCIDevice *d; + PCIBridge *br; + DeviceState *qdev; + + d = pci_create_multifunction(bus, devfn, multifunction, + PCIE_DOWNSTREAM_PORT); + if (!d) { + return NULL; + } + br = DO_UPCAST(PCIBridge, dev, d); + + qdev = &br->dev.qdev; + pci_bridge_map_irq(br, bus_name, map_irq); + qdev_prop_set_uint8(qdev, "port", port); + qdev_prop_set_uint8(qdev, "chassis", chassis); + qdev_prop_set_uint16(qdev, "slot", slot); + qdev_init_nofail(qdev); + + return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br)); +} + +static const VMStateDescription vmstate_pcie_downstream = { + .name = "pcie-downstream-port", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), + VMSTATE_STRUCT(port.br.dev.aer_log, PCIESlot, 0, vmstate_pcie_aer_log, + struct pcie_aer_log), + VMSTATE_END_OF_LIST() + } +}; + +static PCIDeviceInfo pcie_downstream_info = { + .qdev.name = PCIE_DOWNSTREAM_PORT, + .qdev.desc = "Downstream Port of PCI Express Switch", + .qdev.size = sizeof(PCIESlot), + .qdev.reset = pcie_downstream_reset, + .qdev.vmsd = &vmstate_pcie_downstream, + + .is_express = 1, + .is_bridge = 1, + .config_write = pcie_downstream_write_config, + .init = pcie_downstream_initfn, + .exit = pcie_downstream_exitfn, + + .qdev.props = (Property[]) { + DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), + DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), + DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), + DEFINE_PROP_UINT16("aer_log_max", PCIESlot, + port.br.dev.aer_log.log_max, + PCIE_AER_LOG_MAX_DEFAULT), + DEFINE_PROP_END_OF_LIST(), + } +}; + +static void pcie_downstream_register(void) +{ + pci_qdev_register(&pcie_downstream_info); +} + +device_init(pcie_downstream_register); + +/* + * Local variables: + * c-indent-level: 4 + * c-basic-offset: 4 + * tab-width: 8 + * indent-tab-mode: nil + * End: + */ diff --git a/hw/pcie_downstream.h b/hw/pcie_downstream.h new file mode 100644 index 0000000..686fdac --- /dev/null +++ b/hw/pcie_downstream.h @@ -0,0 +1,33 @@ +/* + * pcie_downstream.h + * + * Copyright (c) 2010 Isaku Yamahata + * VA Linux Systems Japan K.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef QEMU_PCIE_DOWNSTREAM_H +#define QEMU_PCIE_DOWNSTREAM_H + +#include "pcie_port.h" + +#define PCIE_DOWNSTREAM_PORT "pcie-downstream-port" + +PCIESlot *pcie_downstream_init(PCIBus *bus, + int devfn, bool multifunction, + const char *bus_name, pci_map_irq_fn map_irq, + uint8_t port, uint8_t chassis, uint16_t slot); + +#endif /* QEMU_PCIE_DOWNSTREAM_H */