From patchwork Mon Sep 6 07:46:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Isaku Yamahata X-Patchwork-Id: 63881 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from lists.gnu.org (lists.gnu.org [199.232.76.165]) (using TLSv1 with cipher DHE-RSA-AES256-SHA (256/256 bits)) (Client did not present a certificate) by ozlabs.org (Postfix) with ESMTPS id ED4F4B70DF for ; Mon, 6 Sep 2010 17:41:48 +1000 (EST) Received: from localhost ([127.0.0.1]:50151 helo=lists.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OsWKm-0005DY-US for incoming@patchwork.ozlabs.org; Mon, 06 Sep 2010 03:41:44 -0400 Received: from [140.186.70.92] (port=37910 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OsWCN-0000Mu-Tb for qemu-devel@nongnu.org; Mon, 06 Sep 2010 03:33:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OsWCL-0005lU-Dk for qemu-devel@nongnu.org; Mon, 06 Sep 2010 03:33:03 -0400 Received: from mail.valinux.co.jp ([210.128.90.3]:42919) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OsWCK-0005ks-MU for qemu-devel@nongnu.org; Mon, 06 Sep 2010 03:33:01 -0400 Received: from ps.local.valinux.co.jp (vagw.valinux.co.jp [210.128.90.14]) by mail.valinux.co.jp (Postfix) with SMTP id F23FC107A7E; Mon, 6 Sep 2010 16:32:55 +0900 (JST) Received: (nullmailer pid 21927 invoked by uid 1000); Mon, 06 Sep 2010 07:46:28 -0000 From: Isaku Yamahata To: qemu-devel@nongnu.org Date: Mon, 6 Sep 2010 16:46:24 +0900 Message-Id: X-Mailer: git-send-email 1.7.1.1 In-Reply-To: References: In-Reply-To: References: X-Virus-Scanned: clamav-milter 0.95.2 at va-mail.local.valinux.co.jp X-Virus-Status: Clean X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.6 (newer, 3) Cc: skandasa@cisco.com, etmartin@cisco.com, wexu2@cisco.com, mst@redhat.com, adhyas@gmail.com, yamahata@valinux.co.jp Subject: [Qemu-devel] [PATCH 10/14] pcie root port: implement pcie root port. X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.5 Precedence: list List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org pcie root port. Signed-off-by: Isaku Yamahata --- Makefile.objs | 2 +- hw/pcie_root.c | 247 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ hw/pcie_root.h | 32 +++++++ 3 files changed, 280 insertions(+), 1 deletions(-) create mode 100644 hw/pcie_root.c create mode 100644 hw/pcie_root.h diff --git a/Makefile.objs b/Makefile.objs index c73d12b..658c399 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -186,7 +186,7 @@ hw-obj-$(CONFIG_PIIX4) += piix4.o # PCI watchdog devices hw-obj-y += wdt_i6300esb.o -hw-obj-y += pcie.o pcie_port.o +hw-obj-y += pcie.o pcie_port.o pcie_root.o hw-obj-y += msix.o msi.o # PCI network cards diff --git a/hw/pcie_root.c b/hw/pcie_root.c new file mode 100644 index 0000000..cecfc6e --- /dev/null +++ b/hw/pcie_root.c @@ -0,0 +1,247 @@ +/* + * pcie_root.c + * + * Copyright (c) 2010 Isaku Yamahata + * VA Linux Systems Japan K.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#include "pci_ids.h" +#include "msi.h" +#include "pcie.h" +#include "pcie_root.h" + +/* For now, Intel X58 IOH corporate deice exporess* root port. + need to get its own id? */ +#define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */ +#define PCI_DEVICE_ID_IOH_REV 0x2 +#define IOH_EP_SSVID_OFFSET 0x40 +#define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL +#define IOH_EP_SSVID_SSID 0 +#define IOH_EP_MSI_OFFSET 0x60 +#define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT +#define IOH_EP_MSI_NR_VECTOR 2 +#define IOH_EP_EXP_OFFSET 0x90 +#define IOH_EP_AER_OFFSET 0x100 + +#define PCIE_ROOT_VID PCI_VENDOR_ID_INTEL +#define PCIE_ROOT_DID PCI_DEVICE_ID_IOH_EPORT +#define PCIE_ROOT_REV PCI_DEVICE_ID_IOH_REV +#define PCIE_ROOT_SSVID_OFFSET IOH_EP_SSVID_OFFSET +#define PCIE_ROOT_SVID IOH_EP_SSVID_SVID +#define PCIE_ROOT_SSID IOH_EP_SSVID_SSID +#define PCIE_ROOT_MSI_SUPPORTED_FLAGS IOH_EP_MSI_SUPPORTED_FLAGS +#define PCIE_ROOT_MSI_NR_VECTOR IOH_EP_MSI_NR_VECTOR +#define PCIE_ROOT_MSI_OFFSET IOH_EP_MSI_OFFSET +#define PCIE_ROOT_EXP_OFFSET IOH_EP_EXP_OFFSET +#define PCIE_ROOT_AER_OFFSET IOH_EP_AER_OFFSET + +/* + * If two MSI vector are allocated, Advanced Error Interrupt Message Number + * is 1. otherwise 0. + * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number. + */ +static uint8_t pcie_root_aer_vector(const PCIDevice *d) +{ + switch (msi_nr_allocated_vector(d)) { + case 1: + return 0; + case 2: + return 1; + case 4: + case 8: + case 16: + case 32: + default: + break; + } + abort(); + return 0; +} + +static void pcie_root_aer_vector_update(PCIDevice *d) +{ + pcie_aer_root_set_vector(d, pcie_root_aer_vector(d)); +} + +static void pcie_root_write_config(PCIDevice *d, + uint32_t address, uint32_t val, int len) +{ + uint16_t sltctl = + pci_get_word(d->config + pci_pcie_cap(d) + PCI_EXP_SLTCTL); + uint32_t root_cmd = + pci_get_long(d->config + pcie_aer_cap(d) + PCI_ERR_ROOT_COMMAND); + + pci_bridge_write_config(d, address, val, len); + msi_write_config(d, address, val, len); + pcie_root_aer_vector_update(d); + pcie_cap_deverr_write_config(d, address, val, len); + pcie_cap_slot_write_config(d, address, val, len, sltctl); + pcie_aer_write_config_vbridge(d, address, val, len); + pcie_aer_write_config(d, address, val, len); + pcie_aer_root_write_config(d, address, val, len, root_cmd); +} + +static void pcie_root_reset(DeviceState *qdev) +{ + PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev); + msi_reset(d); + pcie_root_aer_vector_update(d); + pcie_cap_root_reset(d); + pcie_cap_deverr_reset(d); + pcie_cap_slot_reset(d); + pcie_aer_root_reset(d); + pci_bridge_reset(qdev); +} + +static int pcie_root_initfn(PCIDevice *d) +{ + PCIBridge* br = DO_UPCAST(PCIBridge, dev, d); + PCIEPort *p = DO_UPCAST(PCIEPort, br, br); + PCIESlot *s = DO_UPCAST(PCIESlot, port, p); + int rc; + + rc = pci_bridge_initfn(d); + if (rc < 0) { + return rc; + } + + d->config[PCI_REVISION_ID] = PCIE_ROOT_REV; + pcie_port_init_reg(d); + + pci_config_set_vendor_id(d->config, PCIE_ROOT_VID); + pci_config_set_device_id(d->config, PCIE_ROOT_DID); + + rc = pci_bridge_ssvid_init(d, PCIE_ROOT_SSVID_OFFSET, + PCIE_ROOT_SVID, PCIE_ROOT_SSID); + if (rc < 0) { + return rc; + } + rc = msi_init(d, PCIE_ROOT_MSI_OFFSET, + PCIE_ROOT_MSI_NR_VECTOR, PCIE_ROOT_MSI_SUPPORTED_FLAGS); + if (rc < 0) { + return rc; + } + rc = pci_pcie_cap_init(d, PCIE_ROOT_EXP_OFFSET, PCI_EXP_TYPE_ROOT_PORT, + p->port); + if (rc < 0) { + return rc; + } + pcie_cap_deverr_init(d); + pcie_cap_slot_init(d, s->slot); + pcie_chassis_create(s->chassis); + rc = pcie_chassis_add_slot(s); + if (rc < 0) { + return rc; + } + pcie_cap_root_init(d); + rc = pcie_aer_init(d, PCIE_ROOT_AER_OFFSET); + if (rc < 0) { + return rc; + } + pcie_aer_root_init(d); + pcie_root_aer_vector_update(d); + return 0; +} + +static int pcie_root_exitfn(PCIDevice *d) +{ + int rc; + + pcie_aer_exit(d); + msi_uninit(d); + rc = pci_pcie_cap_exit(d); + if (rc < 0) { + return rc; + } + return pci_bridge_exitfn(d); +} + +PCIESlot *pcie_root_init(PCIBus *bus, int devfn, bool multifunction, + const char *bus_name, pci_map_irq_fn map_irq, + uint8_t port, uint8_t chassis, uint16_t slot) +{ + PCIDevice *d; + PCIBridge *br; + DeviceState *qdev; + + d = pci_create_multifunction(bus, devfn, multifunction, PCIE_ROOT_PORT); + if (!d) { + return NULL; + } + br = DO_UPCAST(PCIBridge, dev, d); + + qdev = &br->dev.qdev; + pci_bridge_map_irq(br, bus_name, map_irq); + qdev_prop_set_uint8(qdev, "port", port); + qdev_prop_set_uint8(qdev, "chassis", chassis); + qdev_prop_set_uint16(qdev, "slot", slot); + qdev_init_nofail(qdev); + + return DO_UPCAST(PCIESlot, port, DO_UPCAST(PCIEPort, br, br)); +} + +static const VMStateDescription vmstate_pcie_root = { + .name = "pcie-root-port", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot), + VMSTATE_STRUCT(port.br.dev.aer_log, PCIESlot, 0, vmstate_pcie_aer_log, + struct pcie_aer_log), + VMSTATE_END_OF_LIST() + } +}; + +static PCIDeviceInfo pcie_root_info = { + .qdev.name = PCIE_ROOT_PORT, + .qdev.desc = "Root Port of PCI Express Switch", + .qdev.size = sizeof(PCIESlot), + .qdev.reset = pcie_root_reset, + .qdev.vmsd = &vmstate_pcie_root, + + .is_express = 1, + .is_bridge = 1, + .config_write = pcie_root_write_config, + .init = pcie_root_initfn, + .exit = pcie_root_exitfn, + + .qdev.props = (Property[]) { + DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0), + DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0), + DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0), + DEFINE_PROP_UINT16("aer_log_max", PCIESlot, + port.br.dev.aer_log.log_max, + PCIE_AER_LOG_MAX_DEFAULT), + DEFINE_PROP_END_OF_LIST(), + } +}; + +static void pcie_root_register(void) +{ + pci_qdev_register(&pcie_root_info); +} + +device_init(pcie_root_register); + +/* + * Local variables: + * c-indent-level: 4 + * c-basic-offset: 4 + * tab-width: 8 + * indent-tab-mode: nil + * End: + */ diff --git a/hw/pcie_root.h b/hw/pcie_root.h new file mode 100644 index 0000000..9c5d4d0 --- /dev/null +++ b/hw/pcie_root.h @@ -0,0 +1,32 @@ +/* + * pcie_root.h + * + * Copyright (c) 2010 Isaku Yamahata + * VA Linux Systems Japan K.K. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef QEMU_PCIE_ROOT_H +#define QEMU_PCIE_ROOT_H + +#include "pcie_port.h" + +#define PCIE_ROOT_PORT "pcie-root-port" + +PCIESlot *pcie_root_init(PCIBus *bus, int devfn, bool multifunction, + const char *bus_name, pci_map_irq_fn map_irq, + uint8_t port, uint8_t chassis, uint16_t slot); + +#endif /* QEMU_PCIE_ROOT_H */