[target/71338] : enable mulu for RL78/G10
diff mbox

Message ID xnwplnh2sl.fsf@greed.delorie.com
State New
Headers show

Commit Message

DJ Delorie June 17, 2016, 10:24 p.m. UTC
Reverts https://gcc.gnu.org/ml/gcc-patches/2014-08/msg01538.html - G10
supports MULU but not other multiplication methods.  Committed.

	PR target/71338
	* config/rl78/rl78-expand.c (umulqihi3): Enable for G10.
	* config/rl78/rl78-virtual.c (umulhi3_shift_virt): Likewise.
	(umulqihi3_virt): Likewise.
	* config/rl78/rl78-real.c (umulhi3_shift_real): Likewise.
	(umulqihi3_real): Likewise.

Patch
diff mbox

Index: gcc/config/rl78/rl78-expand.md
===================================================================
--- gcc/config/rl78/rl78-expand.md	(revision 237565)
+++ gcc/config/rl78/rl78-expand.md	(working copy)
@@ -156,13 +156,13 @@ 
 )
 
 (define_expand "umulqihi3"
   [(set (match_operand:HI 0 "register_operand")
         (mult:HI (zero_extend:HI (match_operand:QI 1 "register_operand"))
                  (zero_extend:HI (match_operand:QI 2 "register_operand"))))]
-  "!TARGET_G10"
+  ""
   ""
 )
 
 (define_expand "andqi3"
   [(set (match_operand:QI         0 "rl78_nonimmediate_operand")
 	(and:QI (match_operand:QI 1 "rl78_general_operand")
Index: gcc/config/rl78/rl78-real.md
===================================================================
--- gcc/config/rl78/rl78-real.md	(revision 237565)
+++ gcc/config/rl78/rl78-real.md	(working copy)
@@ -176,23 +176,23 @@ 
 )
 
 (define_insn "*umulhi3_shift_real"
   [(set (match_operand:HI 0 "register_operand" "=A,A")
         (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "0,0")
                  (match_operand:HI 2 "rl78_24_operand" "N,i")))]
-  "rl78_real_insns_ok () && !TARGET_G10"
+  "rl78_real_insns_ok ()"
   "@
    shlw\t%0, 1
    shlw\t%0, 2"
 )
 
 (define_insn "*umulqihi3_real"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=A")
         (mult:HI (zero_extend:HI (match_operand:QI 1 "general_operand" "%a"))
                  (zero_extend:HI (match_operand:QI 2 "general_operand" "x"))))]
-  "rl78_real_insns_ok () && !TARGET_G10"
+  "rl78_real_insns_ok ()"
   "mulu\t%2"
 )
 
 (define_insn "*andqi3_real"
   [(set (match_operand:QI         0 "rl78_nonimmediate_operand"  "=WsfWsaWhlWab,A,R,vWsa")
 	(and:QI (match_operand:QI 1 "rl78_general_operand"       "%0,0,0,0")
Index: gcc/config/rl78/rl78-virt.md
===================================================================
--- gcc/config/rl78/rl78-virt.md	(revision 237565)
+++ gcc/config/rl78/rl78-virt.md	(working copy)
@@ -113,22 +113,22 @@ 
 )
 
 (define_insn "*umulhi3_shift_virt"
   [(set (match_operand:HI          0 "register_operand" "=v")
         (mult:HI (match_operand:HI 1 "rl78_nonfar_operand" "%vim")
                  (match_operand:HI 2 "rl78_24_operand" "Ni")))]
-  "rl78_virt_insns_ok () && !TARGET_G10"
+  "rl78_virt_insns_ok ()"
   "v.mulu\t%0, %1, %2"
   [(set_attr "valloc" "umul")]
 )
 
 (define_insn "*umulqihi3_virt"
   [(set (match_operand:HI                          0 "register_operand" "=v")
         (mult:HI (zero_extend:HI (match_operand:QI 1 "rl78_nonfar_operand" "%vim"))
                  (zero_extend:HI (match_operand:QI 2 "general_operand" "vim"))))]
-  "rl78_virt_insns_ok () && !TARGET_G10"
+  "rl78_virt_insns_ok ()"
   "v.mulu\t%0, %2"
   [(set_attr "valloc" "umul")]
 )
 
 (define_insn "*andqi3_virt"
   [(set (match_operand:QI         0 "rl78_nonimmediate_operand" "=vm,  *Wfr,  vY")