Patchwork [i386] : Trivial: Remove empty preparation statements from splitters ...

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Submitter Uros Bizjak
Date Sept. 3, 2010, 10:08 a.m.
Message ID <AANLkTimfiQ4LfpNJC_=CzfyJH6YjNpKVjkQy+1OR3o5C@mail.gmail.com>
Download mbox | patch
Permalink /patch/63602/
State New
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Uros Bizjak - Sept. 3, 2010, 10:08 a.m.
Hello!

... plus some code movements.

2010-09-03  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md: Remove empty prepartion statements
	from splitters.

Tested on x86_64-pc-linux-gnu, committed to SVN mainline.

Patch

Index: i386.md
===================================================================
--- i386.md	(revision 163797)
+++ i386.md	(working copy)
@@ -1599,50 +1599,6 @@ 
    (set_attr "athlon_decode" "vector")
    (set_attr "amdfam10_decode" "direct")])
 
-;; Move instructions.
-
-(define_expand "movoi"
-  [(set (match_operand:OI 0 "nonimmediate_operand" "")
-	(match_operand:OI 1 "general_operand" ""))]
-  "TARGET_AVX"
-  "ix86_expand_move (OImode, operands); DONE;")
-
-(define_expand "movti"
-  [(set (match_operand:TI 0 "nonimmediate_operand" "")
-	(match_operand:TI 1 "nonimmediate_operand" ""))]
-  "TARGET_64BIT || TARGET_SSE"
-{
-  if (TARGET_64BIT)
-    ix86_expand_move (TImode, operands);
-  else if (push_operand (operands[0], TImode))
-    ix86_expand_push (TImode, operands[1]);
-  else
-    ix86_expand_vector_move (TImode, operands);
-  DONE;
-})
-
-;; This expands to what emit_move_complex would generate if we didn't
-;; have a movti pattern.  Having this avoids problems with reload on
-;; 32-bit targets when SSE is present, but doesn't seem to be harmful
-;; to have around all the time.
-(define_expand "movcdi"
-  [(set (match_operand:CDI 0 "nonimmediate_operand" "")
-	(match_operand:CDI 1 "general_operand" ""))]
-  ""
-{
-  if (push_operand (operands[0], CDImode))
-    emit_move_complex_push (CDImode, operands[0], operands[1]);
-  else
-    emit_move_complex_parts (operands[0], operands[1]);
-  DONE;
-})
-
-(define_expand "mov<mode>"
-  [(set (match_operand:SWI1248x 0 "nonimmediate_operand" "")
-	(match_operand:SWI1248x 1 "general_operand" ""))]
-  ""
-  "ix86_expand_move (<MODE>mode, operands); DONE;")
-
 ;; Push/pop instructions.
 
 (define_insn "*pushdi2_rex64"
@@ -1771,7 +1727,51 @@ 
   "pop{<imodesuffix>}\t%0"
   [(set_attr "type" "pop")
    (set_attr "mode" "<MODE>")])
+
+;; Move instructions.
 
+(define_expand "movoi"
+  [(set (match_operand:OI 0 "nonimmediate_operand" "")
+	(match_operand:OI 1 "general_operand" ""))]
+  "TARGET_AVX"
+  "ix86_expand_move (OImode, operands); DONE;")
+
+(define_expand "movti"
+  [(set (match_operand:TI 0 "nonimmediate_operand" "")
+	(match_operand:TI 1 "nonimmediate_operand" ""))]
+  "TARGET_64BIT || TARGET_SSE"
+{
+  if (TARGET_64BIT)
+    ix86_expand_move (TImode, operands);
+  else if (push_operand (operands[0], TImode))
+    ix86_expand_push (TImode, operands[1]);
+  else
+    ix86_expand_vector_move (TImode, operands);
+  DONE;
+})
+
+;; This expands to what emit_move_complex would generate if we didn't
+;; have a movti pattern.  Having this avoids problems with reload on
+;; 32-bit targets when SSE is present, but doesn't seem to be harmful
+;; to have around all the time.
+(define_expand "movcdi"
+  [(set (match_operand:CDI 0 "nonimmediate_operand" "")
+	(match_operand:CDI 1 "general_operand" ""))]
+  ""
+{
+  if (push_operand (operands[0], CDImode))
+    emit_move_complex_push (CDImode, operands[0], operands[1]);
+  else
+    emit_move_complex_parts (operands[0], operands[1]);
+  DONE;
+})
+
+(define_expand "mov<mode>"
+  [(set (match_operand:SWI1248x 0 "nonimmediate_operand" "")
+	(match_operand:SWI1248x 1 "general_operand" ""))]
+  ""
+  "ix86_expand_move (<MODE>mode, operands); DONE;")
+
 (define_insn "*mov<mode>_xor"
   [(set (match_operand:SWI48 0 "register_operand" "=r")
 	(match_operand:SWI48 1 "const0_operand" ""))
@@ -2572,23 +2572,8 @@ 
   [(set_attr "type" "imov")
    (set_attr "mode" "QI")])
 
-;; Floating point move instructions.
+;; Floating point push instructions.
 
-(define_expand "movtf"
-  [(set (match_operand:TF 0 "nonimmediate_operand" "")
-	(match_operand:TF 1 "nonimmediate_operand" ""))]
-  "TARGET_SSE2"
-{
-  ix86_expand_move (TFmode, operands);
-  DONE;
-})
-
-(define_expand "mov<mode>"
-  [(set (match_operand:X87MODEF 0 "nonimmediate_operand" "")
-	(match_operand:X87MODEF 1 "general_operand" ""))]
-  ""
-  "ix86_expand_move (<MODE>mode, operands); DONE;")
-
 (define_insn "*pushtf"
   [(set (match_operand:TF 0 "push_operand" "=<,<,<")
 	(match_operand:TF 1 "general_no_elim_operand" "x,Fo,*r"))]
@@ -2614,8 +2599,7 @@ 
 	(match_operand:TF 1 "any_fp_register_operand" ""))]
   "TARGET_SSE2"
   [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -16)))
-   (set (mem:TF (reg:P SP_REG)) (match_dup 1))]
-  "")
+   (set (mem:TF (reg:P SP_REG)) (match_dup 1))])
 
 (define_insn "*pushxf"
   [(set (match_operand:XF 0 "push_operand" "=<,<")
@@ -2698,8 +2682,7 @@ 
 	(match_operand:DF 1 "any_fp_register_operand" ""))]
   "reload_completed"
   [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (const_int -8)))
-   (set (mem:DF (reg:P SP_REG)) (match_dup 1))]
-  "")
+   (set (mem:DF (reg:P SP_REG)) (match_dup 1))])
 
 (define_split
   [(set (match_operand:DF 0 "push_operand" "")
@@ -2752,7 +2735,24 @@ 
   [(set (reg:P SP_REG) (plus:P (reg:P SP_REG) (match_dup 2)))
    (set (mem:SF (reg:P SP_REG)) (match_dup 1))]
   "operands[2] = GEN_INT (-GET_MODE_SIZE (<MODE>mode));")
+
+;; Floating point move instructions.
 
+(define_expand "movtf"
+  [(set (match_operand:TF 0 "nonimmediate_operand" "")
+	(match_operand:TF 1 "nonimmediate_operand" ""))]
+  "TARGET_SSE2"
+{
+  ix86_expand_move (TFmode, operands);
+  DONE;
+})
+
+(define_expand "mov<mode>"
+  [(set (match_operand:X87MODEF 0 "nonimmediate_operand" "")
+	(match_operand:X87MODEF 1 "general_operand" ""))]
+  ""
+  "ix86_expand_move (<MODE>mode, operands); DONE;")
+
 (define_insn "*movtf_internal"
   [(set (match_operand:TF 0 "nonimmediate_operand" "=x,m,x,?r,?o")
 	(match_operand:TF 1 "general_operand" "xm,x,C,roF,Fr"))]
@@ -3199,6 +3199,7 @@ 
     case 3:
     case 4:
       return "#";
+
     case 5:
       switch (get_attr_mode (insn))
 	{
@@ -3750,8 +3751,7 @@ 
   "reload_completed
    && true_regnum (operands[0]) == true_regnum (operands[1])"
   [(parallel [(set (match_dup 0) (and:SWI24 (match_dup 0) (const_int 255)))
-	      (clobber (reg:CC FLAGS_REG))])]
-  "")
+	      (clobber (reg:CC FLAGS_REG))])])
 
 ;; Sign extension instructions
 
@@ -4328,9 +4328,7 @@ 
   "reload_completed"
   [(set (match_dup 2) (match_dup 1))
    (set (match_dup 0) (match_dup 2))]
-{
-  operands[1] = gen_rtx_REG (SFmode, true_regnum (operands[1]));
-})
+  "operands[1] = gen_rtx_REG (SFmode, true_regnum (operands[1]));")
 
 ;; Conversion from XFmode to {SF,DF}mode
 
@@ -4411,8 +4409,7 @@ 
    (clobber (match_operand:MODEF 2 "memory_operand" ""))]
   "TARGET_80387 && reload_completed"
   [(set (match_dup 2) (float_truncate:MODEF (match_dup 1)))
-   (set (match_dup 0) (match_dup 2))]
-  "")
+   (set (match_dup 0) (match_dup 2))])
 
 (define_split
   [(set (match_operand:MODEF 0 "memory_operand" "")
@@ -4420,8 +4417,7 @@ 
 	  (match_operand:XF 1 "register_operand" "")))
    (clobber (match_operand:MODEF 2 "memory_operand" ""))]
   "TARGET_80387"
-  [(set (match_dup 0) (float_truncate:MODEF (match_dup 1)))]
-  "")
+  [(set (match_dup 0) (float_truncate:MODEF (match_dup 1)))])
 
 ;; Signed conversion to DImode.
 
@@ -4684,8 +4680,7 @@ 
   "reload_completed"
   [(parallel [(set (match_dup 2) (fix:X87MODEI (match_dup 1)))
 	      (clobber (match_dup 3))])
-   (set (match_dup 0) (match_dup 2))]
-  "")
+   (set (match_dup 0) (match_dup 2))])
 
 (define_split
   [(set (match_operand:X87MODEI 0 "memory_operand" "")
@@ -4694,8 +4689,7 @@ 
    (clobber (match_scratch 3 ""))]
   "reload_completed"
   [(parallel [(set (match_dup 0) (fix:X87MODEI (match_dup 1)))
-	      (clobber (match_dup 3))])]
-  "")
+	      (clobber (match_dup 3))])])
 
 ;; See the comments in i386.h near OPTIMIZE_MODE_SWITCHING for the description
 ;; of the machinery. Please note the clobber of FLAGS_REG. In i387 control
@@ -4776,8 +4770,7 @@ 
 	      (use (match_dup 2))
 	      (use (match_dup 3))
 	      (clobber (match_dup 5))])
-   (set (match_dup 0) (match_dup 4))]
-  "")
+   (set (match_dup 0) (match_dup 4))])
 
 (define_split
   [(set (match_operand:DI 0 "memory_operand" "")
@@ -4790,8 +4783,7 @@ 
   [(parallel [(set (match_dup 0) (fix:DI (match_dup 1)))
 	      (use (match_dup 2))
 	      (use (match_dup 3))
-	      (clobber (match_dup 5))])]
-  "")
+	      (clobber (match_dup 5))])])
 
 (define_insn "fix_trunc<mode>_i387"
   [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
@@ -4830,8 +4822,7 @@ 
   [(parallel [(set (match_dup 4) (fix:X87MODEI12 (match_dup 1)))
 	      (use (match_dup 2))
 	      (use (match_dup 3))])
-   (set (match_dup 0) (match_dup 4))]
-  "")
+   (set (match_dup 0) (match_dup 4))])
 
 (define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
@@ -4842,15 +4833,15 @@ 
   "reload_completed"
   [(parallel [(set (match_dup 0) (fix:X87MODEI12 (match_dup 1)))
 	      (use (match_dup 2))
-	      (use (match_dup 3))])]
-  "")
+	      (use (match_dup 3))])])
 
 (define_insn "x86_fnstcw_1"
   [(set (match_operand:HI 0 "memory_operand" "=m")
 	(unspec:HI [(reg:HI FPCR_REG)] UNSPEC_FSTCW))]
   "TARGET_80387"
   "fnstcw\t%0"
-  [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
+  [(set (attr "length")
+	(symbol_ref "ix86_attr_length_address_default (insn) + 2"))
    (set_attr "mode" "HI")
    (set_attr "unit" "i387")])
 
@@ -4859,7 +4850,8 @@ 
 	(unspec:HI [(match_operand:HI 0 "memory_operand" "m")] UNSPEC_FLDCW))]
   "TARGET_80387"
   "fldcw\t%0"
-  [(set (attr "length") (symbol_ref "ix86_attr_length_address_default (insn) + 2"))
+  [(set (attr "length")
+	(symbol_ref "ix86_attr_length_address_default (insn) + 2"))
    (set_attr "mode" "HI")
    (set_attr "unit" "i387")
    (set_attr "athlon_decode" "vector")
@@ -4926,8 +4918,7 @@ 
        || TARGET_MIX_SSE_I387)
    && reload_completed"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (float:X87MODEF (match_dup 2)))]
-  "")
+   (set (match_dup 0) (float:X87MODEF (match_dup 2)))])
 
 (define_split
   [(set (match_operand:X87MODEF 0 "register_operand" "")
@@ -4937,8 +4928,7 @@ 
     && (!(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
         || TARGET_MIX_SSE_I387)
     && reload_completed"
-  [(set (match_dup 0) (float:X87MODEF (match_dup 1)))]
-  "")
+  [(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
 
 (define_expand "float<SSEMODEI24:mode><X87MODEF:mode>2"
   [(set (match_operand:X87MODEF 0 "register_operand" "")
@@ -5063,8 +5053,7 @@ 
    && (SSE_REG_P (operands[0])
        || (GET_CODE (operands[0]) == SUBREG
 	   && SSE_REG_P (operands[0])))"
-  [(set (match_dup 0) (float:MODEF (match_dup 1)))]
-  "")
+  [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
 (define_split
   [(set (match_operand:MODEF 0 "register_operand" "")
@@ -5078,8 +5067,7 @@ 
        || (GET_CODE (operands[0]) == SUBREG
 	   && SSE_REG_P (operands[0])))"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (float:MODEF (match_dup 2)))]
-  "")
+   (set (match_dup 0) (float:MODEF (match_dup 2)))])
 
 (define_insn "*float<SSEMODEI24:mode><MODEF:mode>2_mixed_interunit"
   [(set (match_operand:MODEF 0 "register_operand" "=f,x,x")
@@ -5322,8 +5310,7 @@ 
    && (SSE_REG_P (operands[0])
        || (GET_CODE (operands[0]) == SUBREG
 	   && SSE_REG_P (operands[0])))"
-  [(set (match_dup 0) (float:MODEF (match_dup 1)))]
-  "")
+  [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
 (define_insn "*float<SSEMODEI24:mode><MODEF:mode>2_sse_nointerunit"
   [(set (match_operand:MODEF 0 "register_operand" "=x")
@@ -5358,8 +5345,7 @@ 
        || (GET_CODE (operands[0]) == SUBREG
 	   && SSE_REG_P (operands[0])))"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (float:MODEF (match_dup 2)))]
-  "")
+   (set (match_dup 0) (float:MODEF (match_dup 2)))])
 
 (define_split
   [(set (match_operand:MODEF 0 "register_operand" "")
@@ -5371,8 +5357,7 @@ 
    && (SSE_REG_P (operands[0])
        || (GET_CODE (operands[0]) == SUBREG
 	   && SSE_REG_P (operands[0])))"
-  [(set (match_dup 0) (float:MODEF (match_dup 1)))]
-  "")
+  [(set (match_dup 0) (float:MODEF (match_dup 1)))])
 
 (define_insn "*float<SSEMODEI24:mode><X87MODEF:mode>2_i387_with_temp"
   [(set (match_operand:X87MODEF 0 "register_operand" "=f,f")
@@ -5409,8 +5394,7 @@ 
    && reload_completed
    && FP_REG_P (operands[0])"
   [(set (match_dup 2) (match_dup 1))
-   (set (match_dup 0) (float:X87MODEF (match_dup 2)))]
-  "")
+   (set (match_dup 0) (float:X87MODEF (match_dup 2)))])
 
 (define_split
   [(set (match_operand:X87MODEF 0 "register_operand" "")
@@ -5420,8 +5404,7 @@ 
    && X87_ENABLE_FLOAT (<X87MODEF:MODE>mode, <SSEMODEI24:MODE>mode)
    && reload_completed
    && FP_REG_P (operands[0])"
-  [(set (match_dup 0) (float:X87MODEF (match_dup 1)))]
-  "")
+  [(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
 
 ;; Avoid store forwarding (partial memory) stall penalty
 ;; by passing DImode value through XMM registers.  */
@@ -5479,8 +5462,7 @@ 
    && !TARGET_64BIT && optimize_function_for_speed_p (cfun)
    && reload_completed
    && FP_REG_P (operands[0])"
-  [(set (match_dup 0) (float:X87MODEF (match_dup 1)))]
-  "")
+  [(set (match_dup 0) (float:X87MODEF (match_dup 1)))])
 
 ;; Avoid store forwarding (partial memory) stall penalty by extending
 ;; SImode value to DImode through XMM register instead of pushing two
@@ -6050,8 +6032,7 @@ 
   "TARGET_64BIT && reload_completed 
    && true_regnum (operands[0]) != true_regnum (operands[1])"
   [(set (match_dup 0)
-	(plus:DI (match_dup 1) (match_dup 2)))]
-  "")
+	(plus:DI (match_dup 1) (match_dup 2)))])
 
 ;; Convert lea to the lea pattern to avoid flags dependency.
 (define_split
@@ -8840,10 +8821,7 @@ 
    (match_operand:CSGNMODE 2 "register_operand" "")]
   "(SSE_FLOAT_MODE_P (<MODE>mode) && TARGET_SSE_MATH)
    || (TARGET_SSE2 && (<MODE>mode == TFmode))"
-{
-  ix86_expand_copysign (operands);
-  DONE;
-})
+  "ix86_expand_copysign (operands); DONE;")
 
 (define_insn_and_split "copysign<mode>3_const"
   [(set (match_operand:CSGNMODE 0 "register_operand" "=x")
@@ -8857,10 +8835,7 @@ 
   "#"
   "&& reload_completed"
   [(const_int 0)]
-{
-  ix86_split_copysign_const (operands);
-  DONE;
-})
+  "ix86_split_copysign_const (operands); DONE;")
 
 (define_insn "copysign<mode>3_var"
   [(set (match_operand:CSGNMODE 0 "register_operand" "=x,x,x,x,x")
@@ -8888,10 +8863,7 @@ 
     || (TARGET_SSE2 && (<MODE>mode == TFmode)))
    && reload_completed"
   [(const_int 0)]
-{
-  ix86_split_copysign_var (operands);
-  DONE;
-})
+  "ix86_split_copysign_var (operands); DONE;")
 
 ;; One complement instructions
 
@@ -8954,8 +8926,7 @@ 
 		   (match_op_dup 2 [(xor:SWI (match_dup 3) (const_int -1))
 				    (const_int 0)]))
 	      (set (match_dup 1)
-		   (xor:SWI (match_dup 3) (const_int -1)))])]
-  "")
+		   (xor:SWI (match_dup 3) (const_int -1)))])])
 
 ;; ??? Currently never generated - xor is used instead.
 (define_insn "*one_cmplsi2_2_zext"
@@ -8982,8 +8953,7 @@ 
 		   (match_op_dup 2 [(xor:SI (match_dup 3) (const_int -1))
 				    (const_int 0)]))
 	      (set (match_dup 1)
-		   (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])]
-  "")
+		   (zero_extend:DI (xor:SI (match_dup 3) (const_int -1))))])])
 
 ;; Shift instructions
 
@@ -10157,8 +10127,7 @@ 
   && (TARGET_USE_XCHGB || optimize_function_for_size_p (cfun))"
  [(parallel [(set (strict_low_part (match_dup 0))
 		  (bswap:HI (match_dup 0)))
-	     (clobber (reg:CC FLAGS_REG))])]
- "")
+	     (clobber (reg:CC FLAGS_REG))])])
 
 ;; Bit set / bit test instructions
 
@@ -10467,9 +10436,7 @@ 
 	    (const_int 0)))]
   ""
   [(set (match_dup 0) (match_dup 1))]
-{
-  PUT_MODE (operands[1], QImode);
-})
+  "PUT_MODE (operands[1], QImode);")
 
 (define_split
   [(set (strict_low_part (match_operand:QI 0 "nonimmediate_operand" ""))
@@ -10478,9 +10445,7 @@ 
 	    (const_int 0)))]
   ""
   [(set (match_dup 0) (match_dup 1))]
-{
-  PUT_MODE (operands[1], QImode);
-})
+  "PUT_MODE (operands[1], QImode);")
 
 (define_split
   [(set (match_operand:QI 0 "nonimmediate_operand" "")
@@ -10609,9 +10574,7 @@ 
 	(if_then_else (match_dup 0)
 		      (label_ref (match_dup 1))
 		      (pc)))]
-{
-  PUT_MODE (operands[0], VOIDmode);
-})
+  "PUT_MODE (operands[0], VOIDmode);")
 
 (define_split
   [(set (pc)
@@ -13062,8 +13025,7 @@ 
 	(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
   "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
    && !(reload_completed || reload_in_progress)"
-  [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))]
-  "")
+  [(set (match_dup 1) (unspec:XF [(match_dup 2)] UNSPEC_SIN))])
 
 (define_split
   [(set (match_operand:XF 0 "register_operand" "")
@@ -13073,8 +13035,7 @@ 
 	(unspec:XF [(match_dup 2)] UNSPEC_SINCOS_SIN))]
   "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
    && !(reload_completed || reload_in_progress)"
-  [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))]
-  "")
+  [(set (match_dup 0) (unspec:XF [(match_dup 2)] UNSPEC_COS))])
 
 (define_insn "sincos_extend<mode>xf3_i387"
   [(set (match_operand:XF 0 "register_operand" "=f")
@@ -13100,8 +13061,8 @@ 
 	(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
   "find_regno_note (insn, REG_UNUSED, REGNO (operands[0]))
    && !(reload_completed || reload_in_progress)"
-  [(set (match_dup 1) (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))]
-  "")
+  [(set (match_dup 1)
+	(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SIN))])
 
 (define_split
   [(set (match_operand:XF 0 "register_operand" "")
@@ -13112,8 +13073,8 @@ 
 	(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_SINCOS_SIN))]
   "find_regno_note (insn, REG_UNUSED, REGNO (operands[1]))
    && !(reload_completed || reload_in_progress)"
-  [(set (match_dup 0) (unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))]
-  "")
+  [(set (match_dup 0)
+	(unspec:XF [(float_extend:XF (match_dup 2))] UNSPEC_COS))])
 
 (define_expand "sincos<mode>3"
   [(use (match_operand:MODEF 0 "register_operand" ""))
@@ -14112,8 +14073,7 @@ 
   "reload_completed"
   [(parallel [(set (match_dup 2) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
 	      (clobber (match_dup 3))])
-   (set (match_dup 0) (match_dup 2))]
-  "")
+   (set (match_dup 0) (match_dup 2))])
 
 (define_split
   [(set (match_operand:DI 0 "memory_operand" "")
@@ -14123,8 +14083,7 @@ 
    (clobber (match_scratch 3 ""))]
   "reload_completed"
   [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST))
-	      (clobber (match_dup 3))])]
-  "")
+	      (clobber (match_dup 3))])])
 
 (define_insn_and_split "*fist<mode>2_1"
   [(set (match_operand:X87MODEI12 0 "register_operand" "")
@@ -14170,8 +14129,7 @@ 
    (clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
   "reload_completed"
   [(set (match_dup 2) (unspec:X87MODEI12 [(match_dup 1)] UNSPEC_FIST))
-   (set (match_dup 0) (match_dup 2))]
-  "")
+   (set (match_dup 0) (match_dup 2))])
 
 (define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
@@ -14179,8 +14137,7 @@ 
 			   UNSPEC_FIST))
    (clobber (match_operand:X87MODEI12 2 "memory_operand" ""))]
   "reload_completed"
-  [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)] UNSPEC_FIST))]
-  "")
+  [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)] UNSPEC_FIST))])
 
 (define_expand "lrintxf<mode>2"
   [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
@@ -14376,8 +14333,7 @@ 
 	      (use (match_dup 2))
 	      (use (match_dup 3))
 	      (clobber (match_dup 5))])
-   (set (match_dup 0) (match_dup 4))]
-  "")
+   (set (match_dup 0) (match_dup 4))])
 
 (define_split
   [(set (match_operand:DI 0 "memory_operand" "")
@@ -14391,8 +14347,7 @@ 
   [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_FLOOR))
 	      (use (match_dup 2))
 	      (use (match_dup 3))
-	      (clobber (match_dup 5))])]
-  "")
+	      (clobber (match_dup 5))])])
 
 (define_insn "fist<mode>2_floor"
   [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
@@ -14433,8 +14388,7 @@ 
 				  UNSPEC_FIST_FLOOR))
 	      (use (match_dup 2))
 	      (use (match_dup 3))])
-   (set (match_dup 0) (match_dup 4))]
-  "")
+   (set (match_dup 0) (match_dup 4))])
 
 (define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
@@ -14447,8 +14401,7 @@ 
   [(parallel [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
 				  UNSPEC_FIST_FLOOR))
 	      (use (match_dup 2))
-	      (use (match_dup 3))])]
-  "")
+	      (use (match_dup 3))])])
 
 (define_expand "lfloorxf<mode>2"
   [(parallel [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
@@ -14638,8 +14591,7 @@ 
 	      (use (match_dup 2))
 	      (use (match_dup 3))
 	      (clobber (match_dup 5))])
-   (set (match_dup 0) (match_dup 4))]
-  "")
+   (set (match_dup 0) (match_dup 4))])
 
 (define_split
   [(set (match_operand:DI 0 "memory_operand" "")
@@ -14653,8 +14605,7 @@ 
   [(parallel [(set (match_dup 0) (unspec:DI [(match_dup 1)] UNSPEC_FIST_CEIL))
 	      (use (match_dup 2))
 	      (use (match_dup 3))
-	      (clobber (match_dup 5))])]
-  "")
+	      (clobber (match_dup 5))])])
 
 (define_insn "fist<mode>2_ceil"
   [(set (match_operand:X87MODEI12 0 "memory_operand" "=m")
@@ -14695,8 +14646,7 @@ 
 				  UNSPEC_FIST_CEIL))
 	      (use (match_dup 2))
 	      (use (match_dup 3))])
-   (set (match_dup 0) (match_dup 4))]
-  "")
+   (set (match_dup 0) (match_dup 4))])
 
 (define_split
   [(set (match_operand:X87MODEI12 0 "memory_operand" "")
@@ -14709,8 +14659,7 @@ 
   [(parallel [(set (match_dup 0) (unspec:X87MODEI12 [(match_dup 1)]
 				  UNSPEC_FIST_CEIL))
 	      (use (match_dup 2))
-	      (use (match_dup 3))])]
-  "")
+	      (use (match_dup 3))])])
 
 (define_expand "lceilxf<mode>2"
   [(parallel [(set (match_operand:X87MODEI 0 "nonimmediate_operand" "")
@@ -16521,7 +16470,6 @@ 
   "operands[0] = gen_lowpart (SImode, operands[0]);
    operands[2] = gen_lowpart (SImode, operands[2]);
    operands[3] = gen_lowpart (SImode, operands[3]);")
-
 
 ;; RTL Peephole optimizations, run before sched2.  These primarily look to
 ;; transform a complex memory operation into two memory to register operations.