diff mbox

[1/2] gcc/arc: New peephole2 and little endian arc test fixes

Message ID dd9d1b0392b192d009c12874d85020649ff5a8a8.1465946922.git.andrew.burgess@embecosm.com
State New
Headers show

Commit Message

Andrew Burgess June 14, 2016, 11:38 p.m. UTC 
Resolve some test failures introduced for little endian arc as a result
of the recent arc/nps400 additions.

There's a new peephole2 optimisation to merge together two zero_extracts
in order that the movb instruction can be used.

Source operand mode filled in for a peephole2 optimisation, to silence a
build warning.

One of the test cases is extended so that the test does something
meaningful in both big and little endian arc mode.

Other tests have their expected results updated to reflect improvements
in other areas of GCC.

gcc/ChangeLog:

	* config/arc/arc.md (movb peephole2): New peephole2 to merge two
	zero_extract operations to allow a movb to occur.
	(bitops peephole2): Add mode to source operand.

gcc/testsuite/ChangeLog:

	* gcc.target/arc/movb-1.c: Update little endian arc results.
	* gcc.target/arc/movb-2.c: Likewise.
	* gcc.target/arc/movb-5.c: Likewise.
	* gcc.target/arc/movh_cl-1.c: Extend test to cover little endian
	arc.
---
 gcc/ChangeLog                            |  6 ++++++
 gcc/config/arc/arc.md                    | 16 +++++++++++++++-
 gcc/testsuite/ChangeLog                  |  8 ++++++++
 gcc/testsuite/gcc.target/arc/movb-1.c    |  2 +-
 gcc/testsuite/gcc.target/arc/movb-2.c    |  2 +-
 gcc/testsuite/gcc.target/arc/movb-5.c    |  2 +-
 gcc/testsuite/gcc.target/arc/movh_cl-1.c | 11 +++++++++++
 7 files changed, 43 insertions(+), 4 deletions(-)
diff mbox

Patch

diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
index a4ee084..dc57e9b 100644
--- a/gcc/config/arc/arc.md
+++ b/gcc/config/arc/arc.md
@@ -6157,7 +6157,7 @@ 
 	(zero_extract:SI (match_dup 1)
 			 (match_dup 2)
 			 (match_operand:SI 4 "const_int_operand" "")))
-   (set (match_dup 1) (match_operand 8))
+   (set (match_dup 1) (match_operand:SI 8))
    (set (zero_extract:SI (match_dup 0)
 			 (match_operand:SI 5 "const_int_operand" "")
 			 (match_operand:SI 6 "const_int_operand" ""))
@@ -6173,6 +6173,20 @@ 
 		   (zero_extract:SI (match_dup 1) (match_dup 5) (match_dup 7)))])
    (match_dup 1)])
 
+(define_peephole2
+  [(set (match_operand:SI 0 "register_operand" "")
+        (zero_extract:SI (match_dup 0)
+			 (match_operand:SI 1 "const_int_operand" "")
+			 (match_operand:SI 2 "const_int_operand" "")))
+   (set (zero_extract:SI (match_operand:SI 3 "register_operand" "")
+			 (match_dup 1)
+                         (match_dup 2))
+	(match_dup 0))]
+  "TARGET_NPS_BITOPS
+   && !reg_overlap_mentioned_p (operands[0], operands[3])"
+  [(set (zero_extract:SI (match_dup 3) (match_dup 1) (match_dup 2))
+        (zero_extract:SI (match_dup 0) (match_dup 1) (match_dup 2)))])
+
 ;; include the arc-FPX instructions
 (include "fpx.md")
 
diff --git a/gcc/testsuite/gcc.target/arc/movb-1.c b/gcc/testsuite/gcc.target/arc/movb-1.c
index 65d4ba4..94d9f5f 100644
--- a/gcc/testsuite/gcc.target/arc/movb-1.c
+++ b/gcc/testsuite/gcc.target/arc/movb-1.c
@@ -10,4 +10,4 @@  f (void)
   bar.b = foo.b;
 }
 /* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *5, *3, *8" { target arceb-*-* } } } */
-/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *19, *21, *8" { target arc-*-* } } } */
+/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *3, *5, *8" { target arc-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/arc/movb-2.c b/gcc/testsuite/gcc.target/arc/movb-2.c
index 1ba9976..708f393 100644
--- a/gcc/testsuite/gcc.target/arc/movb-2.c
+++ b/gcc/testsuite/gcc.target/arc/movb-2.c
@@ -9,5 +9,5 @@  f (void)
 {
   bar.b = foo.b;
 }
-/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *23, *23, *9" { target arc-*-* } } } */
+/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *7, *7, *9" { target arc-*-* } } } */
 /* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *0, *0, *9" { target arceb-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/arc/movb-5.c b/gcc/testsuite/gcc.target/arc/movb-5.c
index 9dbe8a1..d285888 100644
--- a/gcc/testsuite/gcc.target/arc/movb-5.c
+++ b/gcc/testsuite/gcc.target/arc/movb-5.c
@@ -9,5 +9,5 @@  f (void)
 {
   bar.b = foo.b;
 }
-/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *23, *(23|7), *9" { target arc-*-* } } } */
+/* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *7, *7, *9" { target arc-*-* } } } */
 /* { dg-final { scan-assembler "movb\[ \t\]+r\[0-5\]+, *r\[0-5\]+, *r\[0-5\]+, *0, *0, *9" { target arceb-*-* } } } */
diff --git a/gcc/testsuite/gcc.target/arc/movh_cl-1.c b/gcc/testsuite/gcc.target/arc/movh_cl-1.c
index 220cd9d..c643481 100644
--- a/gcc/testsuite/gcc.target/arc/movh_cl-1.c
+++ b/gcc/testsuite/gcc.target/arc/movh_cl-1.c
@@ -10,6 +10,9 @@  struct thing
     {
       unsigned a : 1;
       unsigned b : 1;
+      unsigned c : 28;
+      unsigned d : 1;
+      unsigned e : 1;
     };
   };
 };
@@ -24,4 +27,12 @@  blah ()
   func (xx.raw);
 }
 
+void
+woof ()
+{
+  struct thing xx;
+  xx.d = xx.e = 1;
+  func (xx.raw);
+}
+
 /* { dg-final { scan-assembler "movh\.cl r\[0-9\]+,0xc0000000>>16" } } */