[PATCHv3,4/7] Documentation: dt: socfpga: Add Arria10 Ethernet binding
diff mbox

Message ID 1465852752-11018-5-git-send-email-tthayer@opensource.altera.com
State Changes Requested, archived
Headers show

Commit Message

tthayer@opensource.altera.com June 13, 2016, 9:19 p.m. UTC
From: Thor Thayer <tthayer@opensource.altera.com>

Add the device tree bindings needed to support the Altera Ethernet
FIFO buffers on the Arria10 chip.

Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
---
v2  No Change
v3  Change to common compatible string based on maintainer comments
    Add local IRQ values.
---
 .../bindings/arm/altera/socfpga-eccmgr.txt         |   24 ++++++++++++++++++++
 1 file changed, 24 insertions(+)

Comments

Rob Herring June 16, 2016, 6:39 p.m. UTC | #1
On Mon, Jun 13, 2016 at 04:19:09PM -0500, tthayer@opensource.altera.com wrote:
> From: Thor Thayer <tthayer@opensource.altera.com>
> 
> Add the device tree bindings needed to support the Altera Ethernet
> FIFO buffers on the Arria10 chip.
> 
> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
> ---
> v2  No Change
> v3  Change to common compatible string based on maintainer comments
>     Add local IRQ values.
> ---
>  .../bindings/arm/altera/socfpga-eccmgr.txt         |   24 ++++++++++++++++++++
>  1 file changed, 24 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
> index 15eb0df..e9febbb 100644
> --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
> @@ -82,6 +82,14 @@ Required Properties:
>  - interrupts : Should be single bit error interrupt, then double bit error
>  	interrupt, in this order.
>  
> +Ethernet FIFO ECC
> +Required Properties:
> +- compatible : Should be "altr,socfpga-eth-mac-ecc"
> +- reg        : Address and size for ECC block registers.
> +- parent     : phandle to parent Ethernet node.

parent is too vague. How about altr,ethernet-mac.

> +- interrupts : Should be single bit error interrupt, then double bit error
> +	interrupt, in this order.
> +
>  Example:
>  
>  	eccmgr: eccmgr@ffd06000 {
> @@ -108,4 +116,20 @@ Example:
>  			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
>  				     <33 IRQ_TYPE_LEVEL_HIGH> ;
>  		};
> +
> +		emac0-rx-ecc@ff8c0800 {
> +			compatible = "altr,socfpga-eth-mac-ecc";
> +			reg = <0xff8c0800 0x400>;
> +			parent = <&gmac0>;
> +			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
> +				     <36 IRQ_TYPE_LEVEL_HIGH>;
> +		};
> +
> +		emac0-tx-ecc@ff8c0c00 {
> +			compatible = "altr,socfpga-eth-mac-ecc";
> +			reg = <0xff8c0c00 0x400>;
> +			parent = <&gmac0>;
> +			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
> +				     <37 IRQ_TYPE_LEVEL_HIGH>;
> +		};
>  	};
> -- 
> 1.7.9.5
> 
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tthayer@opensource.altera.com June 16, 2016, 7:12 p.m. UTC | #2
Hi Rob,

On 06/16/2016 01:39 PM, Rob Herring wrote:
> On Mon, Jun 13, 2016 at 04:19:09PM -0500, tthayer@opensource.altera.com wrote:
>> From: Thor Thayer <tthayer@opensource.altera.com>
>>
>> Add the device tree bindings needed to support the Altera Ethernet
>> FIFO buffers on the Arria10 chip.
>>
>> Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
>> ---
>> v2  No Change
>> v3  Change to common compatible string based on maintainer comments
>>      Add local IRQ values.
>> ---
>>   .../bindings/arm/altera/socfpga-eccmgr.txt         |   24 ++++++++++++++++++++
>>   1 file changed, 24 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>> index 15eb0df..e9febbb 100644
>> --- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>> +++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
>> @@ -82,6 +82,14 @@ Required Properties:
>>   - interrupts : Should be single bit error interrupt, then double bit error
>>   	interrupt, in this order.
>>
>> +Ethernet FIFO ECC
>> +Required Properties:
>> +- compatible : Should be "altr,socfpga-eth-mac-ecc"
>> +- reg        : Address and size for ECC block registers.
>>
>
> parent is too vague. How about altr,ethernet-mac.
>
OK. I'll change to this.

+- parent     : phandle to parent altr,ethernet-mac node

Thanks for reviewing!

>> +- interrupts : Should be single bit error interrupt, then double bit error
>> +	interrupt, in this order.
>> +
>>   Example:
>>
>>   	eccmgr: eccmgr@ffd06000 {
>> @@ -108,4 +116,20 @@ Example:
>>   			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
>>   				     <33 IRQ_TYPE_LEVEL_HIGH> ;
>>   		};
>> +
>> +		emac0-rx-ecc@ff8c0800 {
>> +			compatible = "altr,socfpga-eth-mac-ecc";
>> +			reg = <0xff8c0800 0x400>;
>> +			parent = <&gmac0>;
>> +			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <36 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>> +
>> +		emac0-tx-ecc@ff8c0c00 {
>> +			compatible = "altr,socfpga-eth-mac-ecc";
>> +			reg = <0xff8c0c00 0x400>;
>> +			parent = <&gmac0>;
>> +			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
>> +				     <37 IRQ_TYPE_LEVEL_HIGH>;
>> +		};
>>   	};
>> --
>> 1.7.9.5
>>
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Patch
diff mbox

diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
index 15eb0df..e9febbb 100644
--- a/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
+++ b/Documentation/devicetree/bindings/arm/altera/socfpga-eccmgr.txt
@@ -82,6 +82,14 @@  Required Properties:
 - interrupts : Should be single bit error interrupt, then double bit error
 	interrupt, in this order.
 
+Ethernet FIFO ECC
+Required Properties:
+- compatible : Should be "altr,socfpga-eth-mac-ecc"
+- reg        : Address and size for ECC block registers.
+- parent     : phandle to parent Ethernet node.
+- interrupts : Should be single bit error interrupt, then double bit error
+	interrupt, in this order.
+
 Example:
 
 	eccmgr: eccmgr@ffd06000 {
@@ -108,4 +116,20 @@  Example:
 			interrupts = <1 IRQ_TYPE_LEVEL_HIGH>,
 				     <33 IRQ_TYPE_LEVEL_HIGH> ;
 		};
+
+		emac0-rx-ecc@ff8c0800 {
+			compatible = "altr,socfpga-eth-mac-ecc";
+			reg = <0xff8c0800 0x400>;
+			parent = <&gmac0>;
+			interrupts = <4 IRQ_TYPE_LEVEL_HIGH>,
+				     <36 IRQ_TYPE_LEVEL_HIGH>;
+		};
+
+		emac0-tx-ecc@ff8c0c00 {
+			compatible = "altr,socfpga-eth-mac-ecc";
+			reg = <0xff8c0c00 0x400>;
+			parent = <&gmac0>;
+			interrupts = <5 IRQ_TYPE_LEVEL_HIGH>,
+				     <37 IRQ_TYPE_LEVEL_HIGH>;
+		};
 	};