From patchwork Thu Sep 2 09:20:24 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Mingjie Xing X-Patchwork-Id: 63461 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id C7AE5B715F for ; Thu, 2 Sep 2010 19:20:37 +1000 (EST) Received: (qmail 3929 invoked by alias); 2 Sep 2010 09:20:33 -0000 Received: (qmail 3914 invoked by uid 22791); 2 Sep 2010 09:20:31 -0000 X-SWARE-Spam-Status: No, hits=-1.9 required=5.0 tests=AWL, BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, T_TO_NO_BRKTS_FREEMAIL X-Spam-Check-By: sourceware.org Received: from mail-yw0-f47.google.com (HELO mail-yw0-f47.google.com) (209.85.213.47) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Thu, 02 Sep 2010 09:20:26 +0000 Received: by ywa8 with SMTP id 8so110172ywa.20 for ; Thu, 02 Sep 2010 02:20:25 -0700 (PDT) MIME-Version: 1.0 Received: by 10.150.242.24 with SMTP id p24mr4746404ybh.380.1283419224910; Thu, 02 Sep 2010 02:20:24 -0700 (PDT) Received: by 10.151.144.7 with HTTP; Thu, 2 Sep 2010 02:20:24 -0700 (PDT) In-Reply-To: <87lj7lqr7c.fsf@firetop.home> References: <87occkt2qv.fsf@firetop.home> <87lj7lqr7c.fsf@firetop.home> Date: Thu, 2 Sep 2010 17:20:24 +0800 Message-ID: Subject: Re: [mips] Change the definition of macro SHIFT_COUNT_TRUNCATED From: Mingjie Xing To: gcc-patches@gcc.gnu.org, rdsandiford@googlemail.com X-IsSubscribed: yes Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org 2010/9/2 Richard Sandiford : > It's far from ideal, but I suppose we have to go with it. > Can you post the complete patch? Sure. See the attachment. gcc/ChangeLog * config/mips/mips.h (SHIFT_COUNT_TRUNCATED): Change the definition. * config/mips/mips.c (mips_shift_truncation_mask): Implement TARGET_SHIFT_TRUNCATION_MASK. gcc/testsuite/ChangeLog * gcc.target/mips/loongson-shift-count-truncated-1.c: New. Is it OK? Thanks, Mingjie Index: testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c =================================================================== --- testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c (revision 0) +++ testsuite/gcc.target/mips/loongson-shift-count-truncated-1.c (revision 0) @@ -0,0 +1,35 @@ +/* Test case for SHIFT_COUNT_TRUNCATED on Loongson. */ + +/* { dg-do run } */ +/* loongson.h does not handle or check for MIPS16ness. There doesn't + seem any good reason for it to, given that the Loongson processors + do not support MIPS16. */ +/* { dg-options "isa=loongson -mhard-float -mno-mips16 -O1" } */ + +#include "loongson.h" +#include + +typedef union { int32x2_t v; int32_t a[2]; } int32x2_encap_t; + +void +main1 (int shift) +{ + int32x2_encap_t s; + int32x2_encap_t r; + + s.a[0] = 0xffffffff; + s.a[1] = 0xffffffff; + /* Loongson SIMD use low-order 7 bits to specify the shift amount. Thus + V2SI << 0x40 == 0. The below expression 'shift & 0x3f' will be mis-optimized + as 'shift', if SHIFT_COUNT_TRUNCATED is nonzero. */ + r.v = psllw_s (s.v, (shift & 0x3f)); + assert (r.a[0] == 0xffffffff); + assert (r.a[1] == 0xffffffff); +} + +int +main (void) +{ + main1 (0x40); + return 0; +} Index: config/mips/mips.c =================================================================== --- config/mips/mips.c (revision 163495) +++ config/mips/mips.c (working copy) @@ -16335,6 +16335,20 @@ void mips_function_profiler (FILE *file) fprintf (file, "\tmove\t%s,%s\n", reg_names[STATIC_CHAIN_REGNUM], reg_names[2]); } + +/* Implement TARGET_SHIFT_TRUNCATION_MASK. We want to keep the current + behaviour of TARGET_SHIFT_TRUNCATION_MASK for non-vector modes even + when TARGET_LOONGSON_2EF is true. */ + +static unsigned HOST_WIDE_INT +mips_shift_truncation_mask (enum machine_mode mode) +{ + if (TARGET_LOONGSON_2EF && VECTOR_MODE_P (mode)) + return 0; + + return GET_MODE_BITSIZE (mode) - 1; +} + /* Initialize the GCC target structure. */ #undef TARGET_ASM_ALIGNED_HI_OP @@ -16539,6 +16553,9 @@ void mips_function_profiler (FILE *file) #undef TARGET_ASM_OUTPUT_SOURCE_FILENAME #define TARGET_ASM_OUTPUT_SOURCE_FILENAME mips_output_filename +#undef TARGET_SHIFT_TRUNCATION_MASK +#define TARGET_SHIFT_TRUNCATION_MASK mips_shift_truncation_mask + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-mips.h" Index: config/mips/mips.h =================================================================== --- config/mips/mips.h (revision 163495) +++ config/mips/mips.h (working copy) @@ -2446,7 +2446,7 @@ typedef struct mips_args { /* Define this to be nonzero if shift instructions ignore all but the low-order few bits. */ -#define SHIFT_COUNT_TRUNCATED 1 +#define SHIFT_COUNT_TRUNCATED (TARGET_LOONGSON_2EF ? 0 : 1) /* Value is 1 if truncating an integer of INPREC bits to OUTPREC bits is done just by pretending it is already truncated. */