[2/2] e1000e: correct MAC-PHY interconnect register offset for 82579
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Message ID 9d7ed2714d4812499c29c1c9285388d56b8922e5.1283391991.git.leann.ogasawara@canonical.com
State Accepted
Delegated to: Leann Ogasawara
Headers show

Commit Message

Leann Ogasawara Sept. 2, 2010, 2:09 a.m. UTC
BugLink: https://bugs.launchpad.net/bugs/601044

The MAC-PHY interconnect register set on ICH/PCH parts is accessed through
a peephole mechanism by writing an offset to a CSR register.  The offset
for the interconnect's half-duplex control register (which is used in a
jumbo frame workaround for 82579) is incorrect.

Signed-off-by: Bruce Allan <bruce.w.allan@intel.com>
Tested-by: Jeff Pieper <jeffrey.e.pieper@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
(cherry picked from commit 96f2bd13bfb6df5beec7fe55405ad94b528b8b4c)

Signed-off-by: Leann Ogasawara <leann.ogasawara@canonical.com>
 drivers/net/e1000e/hw.h |    2 +-
 1 files changed, 1 insertions(+), 1 deletions(-)

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diff --git a/drivers/net/e1000e/hw.h b/drivers/net/e1000e/hw.h
index deec3a4..76febe4 100644
--- a/drivers/net/e1000e/hw.h
+++ b/drivers/net/e1000e/hw.h
@@ -313,7 +313,7 @@  enum e1e_registers {
 #define E1000_KMRNCTRLSTA_DIAG_NELPBK	0x1000 /* Nearend Loopback mode */
 #define E1000_KMRNCTRLSTA_K1_CONFIG	0x7
 #define E1000_KMRNCTRLSTA_K1_ENABLE	0x0002
-#define E1000_KMRNCTRLSTA_HD_CTRL	0x0002
+#define E1000_KMRNCTRLSTA_HD_CTRL	0x10   /* Kumeran HD Control */
 #define IFE_PHY_SPECIAL_CONTROL		0x11 /* 100BaseTx PHY Special Control */