| Message ID | 1465387659-30011-4-git-send-email-bmeng.cn@gmail.com |
|---|---|
| State | Accepted |
| Commit | 58d1fedb1f7d1a65918dcdc82c53f83b4c813368 |
| Delegated to: | Bin Meng |
| Headers | show |
On 08.06.2016 14:07, Bin Meng wrote: > At present all BayTrail boards configure fsp,emmc-boot-mode to 2, > which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1 > only shows up on some early stepping silicon of BayTrail SoC. > Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP > provides a config option fsp,emmc-boot-mode which tells FSP which > eMMC controller it initializes. Instead of hardcoded to 2, now > we change it to 1 which means "auto". > > With this change, MinnowMax board (with a D0 stepping BayTrail SoC) > can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot > 'pci' command. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Thanks, Stefan
On 8 June 2016 at 06:07, Bin Meng <bmeng.cn@gmail.com> wrote: > At present all BayTrail boards configure fsp,emmc-boot-mode to 2, > which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1 > only shows up on some early stepping silicon of BayTrail SoC. > Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP > provides a config option fsp,emmc-boot-mode which tells FSP which > eMMC controller it initializes. Instead of hardcoded to 2, now > we change it to 1 which means "auto". > > With this change, MinnowMax board (with a D0 stepping BayTrail SoC) > can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot > 'pci' command. > > Signed-off-by: Bin Meng <bmeng.cn@gmail.com> > --- > > arch/x86/dts/bayleybay.dts | 2 +- > arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +- > arch/x86/dts/minnowmax.dts | 2 +- > 3 files changed, 3 insertions(+), 3 deletions(-) Reviewed-by: Simon Glass <sjg@chromium.org>
On Fri, Jun 10, 2016 at 8:35 AM, Simon Glass <sjg@chromium.org> wrote: > On 8 June 2016 at 06:07, Bin Meng <bmeng.cn@gmail.com> wrote: >> At present all BayTrail boards configure fsp,emmc-boot-mode to 2, >> which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1 >> only shows up on some early stepping silicon of BayTrail SoC. >> Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP >> provides a config option fsp,emmc-boot-mode which tells FSP which >> eMMC controller it initializes. Instead of hardcoded to 2, now >> we change it to 1 which means "auto". >> >> With this change, MinnowMax board (with a D0 stepping BayTrail SoC) >> can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot >> 'pci' command. >> >> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> >> --- >> >> arch/x86/dts/bayleybay.dts | 2 +- >> arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +- >> arch/x86/dts/minnowmax.dts | 2 +- >> 3 files changed, 3 insertions(+), 3 deletions(-) > > Reviewed-by: Simon Glass <sjg@chromium.org> applied to u-boot-x86, thanks!
diff --git a/arch/x86/dts/bayleybay.dts b/arch/x86/dts/bayleybay.dts index 536049b..1c2f671 100644 --- a/arch/x86/dts/bayleybay.dts +++ b/arch/x86/dts/bayleybay.dts @@ -218,7 +218,7 @@ fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <2>; + fsp,emmc-boot-mode = <1>; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; diff --git a/arch/x86/dts/conga-qeval20-qa3-e3845.dts b/arch/x86/dts/conga-qeval20-qa3-e3845.dts index 7e69ba4..1e14c8b 100644 --- a/arch/x86/dts/conga-qeval20-qa3-e3845.dts +++ b/arch/x86/dts/conga-qeval20-qa3-e3845.dts @@ -218,7 +218,7 @@ fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <2>; + fsp,emmc-boot-mode = <1>; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1; diff --git a/arch/x86/dts/minnowmax.dts b/arch/x86/dts/minnowmax.dts index fda170c..ba96e36 100644 --- a/arch/x86/dts/minnowmax.dts +++ b/arch/x86/dts/minnowmax.dts @@ -247,7 +247,7 @@ fsp,mrc-init-mmio-size = <0x800>; fsp,mrc-init-spd-addr1 = <0xa0>; fsp,mrc-init-spd-addr2 = <0xa2>; - fsp,emmc-boot-mode = <2>; + fsp,emmc-boot-mode = <1>; fsp,enable-sdio; fsp,enable-sdcard; fsp,enable-hsuart1;
At present all BayTrail boards configure fsp,emmc-boot-mode to 2, which means "eMMC 4.1" per FSP documentation. However, eMMC 4.1 only shows up on some early stepping silicon of BayTrail SoC. Newer stepping SoC integrates an eMMC 4.5 controller. Intel FSP provides a config option fsp,emmc-boot-mode which tells FSP which eMMC controller it initializes. Instead of hardcoded to 2, now we change it to 1 which means "auto". With this change, MinnowMax board (with a D0 stepping BayTrail SoC) can see the eMMC 4.5 controller at PCI address 00.17.00 via U-Boot 'pci' command. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> --- arch/x86/dts/bayleybay.dts | 2 +- arch/x86/dts/conga-qeval20-qa3-e3845.dts | 2 +- arch/x86/dts/minnowmax.dts | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-)