diff mbox

, Add PowerPC ISA 3.0 MTVSRDD support

Message ID 20160531234955.GA5527@ibm-tiger.the-meissners.org
State New
Headers show

Commit Message

Michael Meissner May 31, 2016, 11:49 p.m. UTC 
This patch adds support to issue the MTVSRDD on 64-bit ISA 3.0 systems when the
compiler has a 64-bit value in a GPR, and it wants to create a vector that has
the 64-bit value in both sides of the 128-bit value.

In addition, I simplified the alternatives, eliminating the use of separate
alternatives for a preferred register class and a normal register class.  This
is similar to the change I did for the 128-bit moves previously.

I have done bootstraps on a little endian power8 system with no regressions,
and I have a run on a big endian power7 system in progress.  Assuming the
power7 system does not introduce any new errors, is this patch ok to install in
the trunk.  I also plan to install the patch in the 6.2 branch when the other
ISA 3.0 patches are back ported.

[gcc]
2016-05-31  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* config/rs6000/vsx.md (vsx_splat_<mode>, V2DI/V2DF): Simplify
	alternatives, eliminating preferred register class.  Add support
	for the MTVSRDD instruction in ISA 3.0.
	(vsx_splat_v4si_internal): Use splat_input_operand instead of
	reg_or_indexed_operand.
	(vsx_splat_v4sf_internal): Likewise.

[gcc/testsuite]
2016-05-31  Michael Meissner  <meissner@linux.vnet.ibm.com>

	* gcc.target/powerpc/p9-splat-4.c: New test.

Comments

Segher Boessenkool June 1, 2016, 6:36 p.m. UTC | #1 
On Tue, May 31, 2016 at 07:49:55PM -0400, Michael Meissner wrote:
> This patch adds support to issue the MTVSRDD on 64-bit ISA 3.0 systems when the
> compiler has a 64-bit value in a GPR, and it wants to create a vector that has
> the 64-bit value in both sides of the 128-bit value.

>  ;; V2DF/V2DI splat
>  (define_insn "vsx_splat_<mode>"
> -  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?<VSa>,?<VSa>,?<VSa>")
> +  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>,<VSa>,we")
>  	(vec_duplicate:VSX_D
> -	 (match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,f,Z,<VSa>,<VSa>,Z")))]
> +	 (match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,Z,r")))]
>    "VECTOR_MEM_VSX_P (<MODE>mode)"
>    "@
>     xxpermdi %x0,%x1,%x1,0
> -   xxpermdi %x0,%x1,%x1,0
>     lxvdsx %x0,%y1
> -   xxpermdi %x0,%x1,%x1,0
> -   xxpermdi %x0,%x1,%x1,0
> -   lxvdsx %x0,%y1"
> -  [(set_attr "type" "vecperm,vecperm,vecload,vecperm,vecperm,vecload")])
> +   mtvsrdd %x0,%1,%1"
> +  [(set_attr "type" "vecperm,vecload,mftgpr")])

It should use "b" instead of "r" for the mtvsrdd case.

Okay for trunk with that change, after retesting.  Okay for 6 later, too.

Thanks,


Segher
diff mbox

Patch

Index: gcc/config/rs6000/vsx.md
===================================================================
--- gcc/config/rs6000/vsx.md	(.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/config/rs6000)	(revision 236935)
+++ gcc/config/rs6000/vsx.md	(.../gcc/config/rs6000)	(working copy)
@@ -2384,18 +2384,15 @@  (define_expand "vsx_mergeh_<mode>"
 
 ;; V2DF/V2DI splat
 (define_insn "vsx_splat_<mode>"
-  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=wd,wd,wd,?<VSa>,?<VSa>,?<VSa>")
+  [(set (match_operand:VSX_D 0 "vsx_register_operand" "=<VSa>,<VSa>,we")
 	(vec_duplicate:VSX_D
-	 (match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,f,Z,<VSa>,<VSa>,Z")))]
+	 (match_operand:<VS_scalar> 1 "splat_input_operand" "<VS_64reg>,Z,r")))]
   "VECTOR_MEM_VSX_P (<MODE>mode)"
   "@
    xxpermdi %x0,%x1,%x1,0
-   xxpermdi %x0,%x1,%x1,0
    lxvdsx %x0,%y1
-   xxpermdi %x0,%x1,%x1,0
-   xxpermdi %x0,%x1,%x1,0
-   lxvdsx %x0,%y1"
-  [(set_attr "type" "vecperm,vecperm,vecload,vecperm,vecperm,vecload")])
+   mtvsrdd %x0,%1,%1"
+  [(set_attr "type" "vecperm,vecload,mftgpr")])
 
 ;; V4SI splat (ISA 3.0)
 ;; When SI's are allowed in VSX registers, add XXSPLTW support
@@ -2414,7 +2411,7 @@  (define_expand "vsx_splat_<mode>"
 (define_insn "*vsx_splat_v4si_internal"
   [(set (match_operand:V4SI 0 "vsx_register_operand" "=wa,wa")
 	(vec_duplicate:V4SI
-	 (match_operand:SI 1 "reg_or_indexed_operand" "r,Z")))]
+	 (match_operand:SI 1 "splat_input_operand" "r,Z")))]
   "TARGET_P9_VECTOR"
   "@
    mtvsrws %x0,%1
@@ -2425,7 +2422,7 @@  (define_insn "*vsx_splat_v4si_internal"
 (define_insn_and_split "*vsx_splat_v4sf_internal"
   [(set (match_operand:V4SF 0 "vsx_register_operand" "=wa,wa,wa")
 	(vec_duplicate:V4SF
-	 (match_operand:SF 1 "reg_or_indexed_operand" "Z,wy,r")))]
+	 (match_operand:SF 1 "splat_input_operand" "Z,wy,r")))]
   "TARGET_P9_VECTOR"
   "@
    lxvwsx %x0,%y1

Index: gcc/testsuite/gcc.target/powerpc/p9-splat-4.c
===================================================================
--- gcc/testsuite/gcc.target/powerpc/p9-splat-4.c	(.../svn+ssh://meissner@gcc.gnu.org/svn/gcc/trunk/gcc/testsuite/gcc.target/powerpc)	(revision 0)
+++ gcc/testsuite/gcc.target/powerpc/p9-splat-4.c	(.../gcc/testsuite/gcc.target/powerpc)	(revision 236937)
@@ -0,0 +1,10 @@ 
+/* { dg-do compile { target { powerpc64*-*-* && lp64 } } } */
+/* { dg-skip-if "do not override -mcpu" { powerpc*-*-* } { "-mcpu=*" } { "-mcpu=power9" } } */
+/* { dg-options "-mcpu=power9 -O2" } */
+/* { dg-require-effective-target powerpc_p9vector_ok } */
+
+#include <altivec.h>
+
+vector long long foo (long long a) { return (vector long long) { a, a }; }
+
+/* { dg-final { scan-assembler "mtvsrdd" } } */