| Message ID | 20160531183928.29406-4-bobby.prani@gmail.com |
|---|---|
| State | New |
| Headers | show |
Acked-by: Claudio Fontana <claudio.fontana@huawei.com> On Tuesday, 31 May 2016, Pranith Kumar <bobby.prani@gmail.com> wrote: > Cc: Claudio Fontana <claudio.fontana@gmail.com <javascript:;>> > Signed-off-by: Richard Henderson <rth@twiddle.net <javascript:;>> > Signed-off-by: Pranith Kumar <bobby.prani@gmail.com <javascript:;>> > --- > tcg/aarch64/tcg-target.inc.c | 7 +++++++ > 1 file changed, 7 insertions(+) > > diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c > index 08efdf4..c361a5c 100644 > --- a/tcg/aarch64/tcg-target.inc.c > +++ b/tcg/aarch64/tcg-target.inc.c > @@ -360,6 +360,9 @@ typedef enum { > I3510_EOR = 0x4a000000, > I3510_EON = 0x4a200000, > I3510_ANDS = 0x6a000000, > + > + /* System instructions. */ > + DMB_ISH = 0xd5033bbf, > } AArch64Insn; > > static inline uint32_t tcg_in32(TCGContext *s) > @@ -1625,6 +1628,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); > break; > > + case INDEX_op_mb: > + tcg_out32(s, DMB_ISH); > + break; > case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ > case INDEX_op_mov_i64: > case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ > @@ -1749,6 +1755,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = { > { INDEX_op_muluh_i64, { "r", "r", "r" } }, > { INDEX_op_mulsh_i64, { "r", "r", "r" } }, > > + { INDEX_op_mb, { "r" } }, > { -1 }, > }; > > -- > 2.8.3 > > --
On 05/31/2016 11:39 AM, Pranith Kumar wrote: > + /* System instructions. */ > + DMB_ISH = 0xd5033bbf, ... > + case INDEX_op_mb: > + tcg_out32(s, DMB_ISH); > + break; With the flags argument, this needs to be split. DMB_ISH = 0xd5033b8f DMB_RD = 0x00000010 DMB_WR = 0x00000020 if (a0 == TCG_MB_READ) { a0 = DMB_RD; } else if (a0 == TCG_MB_WRITE) { a0 = DMB_WR; } else { a0 = DMB_RD | DMB_WR; } tcg_out32(s, DMB_ISH | a0); r~
Hi Richard, On Tue, May 31, 2016 at 4:34 PM, Richard Henderson <rth@twiddle.net> wrote: > On 05/31/2016 11:39 AM, Pranith Kumar wrote: >> >> + /* System instructions. */ >> + DMB_ISH = 0xd5033bbf, > > ... >> >> + case INDEX_op_mb: >> + tcg_out32(s, DMB_ISH); >> + break; > > > With the flags argument, this needs to be split. > > DMB_ISH = 0xd5033b8f I just checked this. Shouldn't this be as follows: DMB_ISH = 0xd50338bf DMB_RD = 0x00000100 DMB_WR = 0x00000200 The logic seems to be ok. Thanks! > DMB_RD = 0x00000010 > DMB_WR = 0x00000020 > > if (a0 == TCG_MB_READ) { > a0 = DMB_RD; > } else if (a0 == TCG_MB_WRITE) { > a0 = DMB_WR; > } else { > a0 = DMB_RD | DMB_WR; > } > tcg_out32(s, DMB_ISH | a0); > > > > r~
diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c index 08efdf4..c361a5c 100644 --- a/tcg/aarch64/tcg-target.inc.c +++ b/tcg/aarch64/tcg-target.inc.c @@ -360,6 +360,9 @@ typedef enum { I3510_EOR = 0x4a000000, I3510_EON = 0x4a200000, I3510_ANDS = 0x6a000000, + + /* System instructions. */ + DMB_ISH = 0xd5033bbf, } AArch64Insn; static inline uint32_t tcg_in32(TCGContext *s) @@ -1625,6 +1628,9 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, tcg_out_insn(s, 3508, SMULH, TCG_TYPE_I64, a0, a1, a2); break; + case INDEX_op_mb: + tcg_out32(s, DMB_ISH); + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -1749,6 +1755,7 @@ static const TCGTargetOpDef aarch64_op_defs[] = { { INDEX_op_muluh_i64, { "r", "r", "r" } }, { INDEX_op_mulsh_i64, { "r", "r", "r" } }, + { INDEX_op_mb, { "r" } }, { -1 }, };