| Message ID | 20160531183928.29406-9-bobby.prani@gmail.com |
|---|---|
| State | New |
| Headers | show |
On 31/05/16 21:39, Pranith Kumar wrote: > Cc: Alexander Graf <agraf@suse.de> > Signed-off-by: Richard Henderson <rth@twiddle.net> > Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> > --- > tcg/s390/tcg-target.inc.c | 9 +++++++++ > 1 file changed, 9 insertions(+) > > diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c > index e95b04b..b4f14bc 100644 > --- a/tcg/s390/tcg-target.inc.c > +++ b/tcg/s390/tcg-target.inc.c > @@ -341,6 +341,7 @@ static tcg_insn_unit *tb_ret_addr; > #define FACILITY_EXT_IMM (1ULL << (63 - 21)) > #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) > #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) > +#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND > > static uint64_t facilities; > > @@ -2157,6 +2158,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, > tgen_deposit(s, args[0], args[2], args[3], args[4]); > break; > > + case INDEX_op_mb: > + /* The host memory model is quite strong, we simply need to > + serialize the instruction stream. */ > + tcg_out_insn(s, RR, BCR, > + facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); > + break; > + Do we? What does that mean? Kind regards, Sergey > case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ > case INDEX_op_mov_i64: > case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ > @@ -2278,6 +2286,7 @@ static const TCGTargetOpDef s390_op_defs[] = { > { INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } }, > { INDEX_op_deposit_i64, { "r", "0", "r" } }, > > + { INDEX_op_mb, { "r" } }, > { -1 }, > }; >
On 06/02/2016 12:31 PM, Sergey Fedorov wrote: > On 31/05/16 21:39, Pranith Kumar wrote: >> Cc: Alexander Graf <agraf@suse.de> >> Signed-off-by: Richard Henderson <rth@twiddle.net> >> Signed-off-by: Pranith Kumar <bobby.prani@gmail.com> >> --- >> tcg/s390/tcg-target.inc.c | 9 +++++++++ >> 1 file changed, 9 insertions(+) >> >> diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c >> index e95b04b..b4f14bc 100644 >> --- a/tcg/s390/tcg-target.inc.c >> +++ b/tcg/s390/tcg-target.inc.c >> @@ -341,6 +341,7 @@ static tcg_insn_unit *tb_ret_addr; >> #define FACILITY_EXT_IMM (1ULL << (63 - 21)) >> #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) >> #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) >> +#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND >> >> static uint64_t facilities; >> >> @@ -2157,6 +2158,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, >> tgen_deposit(s, args[0], args[2], args[3], args[4]); >> break; >> >> + case INDEX_op_mb: >> + /* The host memory model is quite strong, we simply need to >> + serialize the instruction stream. */ >> + tcg_out_insn(s, RR, BCR, >> + facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); >> + break; >> + > > Do we? What does that mean? It's the difference between ACQ_REL and SEQ_CST for s390x. FWIW. r~
diff --git a/tcg/s390/tcg-target.inc.c b/tcg/s390/tcg-target.inc.c index e95b04b..b4f14bc 100644 --- a/tcg/s390/tcg-target.inc.c +++ b/tcg/s390/tcg-target.inc.c @@ -341,6 +341,7 @@ static tcg_insn_unit *tb_ret_addr; #define FACILITY_EXT_IMM (1ULL << (63 - 21)) #define FACILITY_GEN_INST_EXT (1ULL << (63 - 34)) #define FACILITY_LOAD_ON_COND (1ULL << (63 - 45)) +#define FACILITY_FAST_BCR_SER FACILITY_LOAD_ON_COND static uint64_t facilities; @@ -2157,6 +2158,13 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc, tgen_deposit(s, args[0], args[2], args[3], args[4]); break; + case INDEX_op_mb: + /* The host memory model is quite strong, we simply need to + serialize the instruction stream. */ + tcg_out_insn(s, RR, BCR, + facilities & FACILITY_FAST_BCR_SER ? 14 : 15, 0); + break; + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ @@ -2278,6 +2286,7 @@ static const TCGTargetOpDef s390_op_defs[] = { { INDEX_op_movcond_i64, { "r", "r", "rC", "r", "0" } }, { INDEX_op_deposit_i64, { "r", "0", "r" } }, + { INDEX_op_mb, { "r" } }, { -1 }, };