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Use flag_general_regs_only with -mgeneral-regs-only

Message ID CAFULd4brcScr9iaJu-MRMqUc_NXX3-Xe9x8B-NfG8ZAWhOChdA@mail.gmail.com
State New
Headers show

Commit Message

Uros Bizjak May 25, 2016, 11:38 a.m. UTC 
On Tue, May 24, 2016 at 11:47 PM, Joseph Myers <joseph@codesourcery.com> wrote:
> On Tue, 24 May 2016, Uros Bizjak wrote:
>
>> > I have thrown together a quick patch that defines target_flags as HOST_WIDE_INT.
>> >
>> > (Patch still needs a small correction, so opth-gen.awk will emit
>> > HOST_WIDE_INT_1 for MASK_* defines, have to go now, but I was able to
>> > compile functional x86_64-apple-darwin15.5.0 crosscompiler.)
>>
>> And here is attached complete (but untested!!) patch that should "just
>> work"(TM).
>
> Have you made sure that cl_host_wide_int gets set for options in
> target_flags, so that get_option_state, option_enabled etc. work correctly
> with such options?

Hm, no ...

Let's leave target_flags in its current state, and add additional
ix86_target_flags.

I'm currently testing attached patch, it also removes two unneded
option variables.

HJ, does this patch work for your?

Uros.

Comments

H.J. Lu May 25, 2016, 5:06 p.m. UTC | #1 
On Wed, May 25, 2016 at 4:38 AM, Uros Bizjak <ubizjak@gmail.com> wrote:
> On Tue, May 24, 2016 at 11:47 PM, Joseph Myers <joseph@codesourcery.com> wrote:
>> On Tue, 24 May 2016, Uros Bizjak wrote:
>>
>>> > I have thrown together a quick patch that defines target_flags as HOST_WIDE_INT.
>>> >
>>> > (Patch still needs a small correction, so opth-gen.awk will emit
>>> > HOST_WIDE_INT_1 for MASK_* defines, have to go now, but I was able to
>>> > compile functional x86_64-apple-darwin15.5.0 crosscompiler.)
>>>
>>> And here is attached complete (but untested!!) patch that should "just
>>> work"(TM).
>>
>> Have you made sure that cl_host_wide_int gets set for options in
>> target_flags, so that get_option_state, option_enabled etc. work correctly
>> with such options?
>
> Hm, no ...
>
> Let's leave target_flags in its current state, and add additional
> ix86_target_flags.
>
> I'm currently testing attached patch, it also removes two unneded
> option variables.
>
> HJ, does this patch work for your?
>

It works.

Thanks.
diff mbox

Patch

diff --git a/gcc/common/config/i386/i386-common.c b/gcc/common/config/i386/i386-common.c
index cc65c8c..4f0a55f 100644
--- a/gcc/common/config/i386/i386-common.c
+++ b/gcc/common/config/i386/i386-common.c
@@ -223,6 +223,11 @@  along with GCC; see the file COPYING3.  If not see
 #define OPTION_MASK_ISA_RDRND_UNSET OPTION_MASK_ISA_RDRND
 #define OPTION_MASK_ISA_F16C_UNSET OPTION_MASK_ISA_F16C
 
+#define OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET \
+  (OPTION_MASK_ISA_MMX_UNSET \
+   | OPTION_MASK_ISA_SSE_UNSET \
+   | OPTION_MASK_ISA_MPX)
+
 /* Implement TARGET_HANDLE_OPTION.  */
 
 bool
@@ -236,6 +241,22 @@  ix86_handle_option (struct gcc_options *opts,
 
   switch (code)
     {
+    case OPT_mgeneral_regs_only:
+      if (value)
+	{
+	  /* Disable MPX, MMX, SSE and x87 instructions if only
+	     general registers are allowed.  */
+	  opts->x_ix86_isa_flags
+	    &= ~OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
+	  opts->x_ix86_isa_flags_explicit
+	    |= OPTION_MASK_ISA_GENERAL_REGS_ONLY_UNSET;
+
+	  opts->x_target_flags &= ~MASK_80387;
+	}
+      else
+	gcc_unreachable ();
+      return true;
+
     case OPT_mmmx:
       if (value)
 	{
diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c
index 51364f3..6a99891 100644
--- a/gcc/config/i386/i386.c
+++ b/gcc/config/i386/i386.c
@@ -5337,7 +5337,10 @@  ix86_option_override_internal (bool main_args_p,
 	    && !(opts->x_ix86_isa_flags_explicit & OPTION_MASK_ISA_PKU))
 	  opts->x_ix86_isa_flags |= OPTION_MASK_ISA_PKU;
 
-	if (!(opts_set->x_target_flags & MASK_80387))
+	/* Don't enable x87 instructions if only
+	   general registers are allowed.  */
+	if (!(opts_set->x_ix86_target_flags & OPTION_MASK_GENERAL_REGS_ONLY)
+	    && !(opts_set->x_target_flags & MASK_80387))
 	  {
 	    if (processor_alias_table[i].flags & PTA_NO_80387)
 	      opts->x_target_flags &= ~MASK_80387;
@@ -6075,7 +6078,6 @@  ix86_function_specific_save (struct cl_target_option *ptr,
   ptr->tune_defaulted = ix86_tune_defaulted;
   ptr->arch_specified = ix86_arch_specified;
   ptr->x_ix86_isa_flags_explicit = opts->x_ix86_isa_flags_explicit;
-  ptr->x_ix86_target_flags_explicit = opts->x_ix86_target_flags_explicit;
   ptr->x_recip_mask_explicit = opts->x_recip_mask_explicit;
   ptr->x_ix86_arch_string = opts->x_ix86_arch_string;
   ptr->x_ix86_tune_string = opts->x_ix86_tune_string;
@@ -6132,7 +6134,6 @@  ix86_function_specific_restore (struct gcc_options *opts,
   ix86_tune_defaulted = ptr->tune_defaulted;
   ix86_arch_specified = ptr->arch_specified;
   opts->x_ix86_isa_flags_explicit = ptr->x_ix86_isa_flags_explicit;
-  opts->x_ix86_target_flags_explicit = ptr->x_ix86_target_flags_explicit;
   opts->x_recip_mask_explicit = ptr->x_recip_mask_explicit;
   opts->x_ix86_arch_string = ptr->x_ix86_arch_string;
   opts->x_ix86_tune_string = ptr->x_ix86_tune_string;
diff --git a/gcc/config/i386/i386.opt b/gcc/config/i386/i386.opt
index 36dd4bd..4b75ba8 100644
--- a/gcc/config/i386/i386.opt
+++ b/gcc/config/i386/i386.opt
@@ -30,6 +30,10 @@  HOST_WIDE_INT ix86_isa_flags = TARGET_64BIT_DEFAULT | TARGET_SUBTARGET_ISA_DEFAU
 Variable
 HOST_WIDE_INT ix86_isa_flags_explicit
 
+; Additional target flags
+Variable
+int ix86_target_flags
+
 TargetVariable
 int recip_mask = RECIP_MASK_DEFAULT
 
@@ -72,14 +76,6 @@  unsigned char branch_cost
 TargetSave
 HOST_WIDE_INT x_ix86_isa_flags_explicit
 
-;; which flags were passed by the user
-Variable
-int ix86_target_flags_explicit
-
-;; which flags were passed by the user
-TargetSave
-HOST_WIDE_INT x_ix86_target_flags_explicit
-
 ;; whether -mtune was not specified
 TargetSave
 unsigned char tune_defaulted
@@ -897,3 +893,7 @@  Enum(stack_protector_guard) String(global) Value(SSP_GLOBAL)
 mmitigate-rop
 Target Var(flag_mitigate_rop) Init(0)
 Attempt to avoid generating instruction sequences containing ret bytes.
+
+mgeneral-regs-only
+Target Report RejectNegative Mask(GENERAL_REGS_ONLY) Var(ix86_target_flags) Save
+Generate code which uses only the general registers.