| Message ID | 1463990479-19403-1-git-send-email-lokeshvutla@ti.com |
|---|---|
| State | Accepted |
| Commit | 9b77b19178446393fce2e74554815c17454f8da8 |
| Delegated to: | Tom Rini |
| Headers | show |
On 05/23/2016 03:01 AM, Lokesh Vutla wrote: > All the output clock parameters of a DPLL needs to be programmed before > locking the DPLL. But it is being configured after locking the DPLL which > could potentially bypass DPLL. So fixing this sequence. > > Reported-by: Richard Woodruff <r-woodruff2@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> > --- > arch/arm/cpu/armv7/omap-common/clocks-common.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c > index ef2ac98..2de9935 100644 > --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c > +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c > @@ -236,6 +236,8 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params, > /* Dpll locked with ideal values for nominal opps. */ > debug("\n %s Dpll already locked with ideal" > "nominal opp values", dpll); > + > + bypass_dpll(base); > goto setup_post_dividers; > } > } > @@ -251,13 +253,13 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params, > > writel(temp, &dpll_regs->cm_clksel_dpll); > > +setup_post_dividers: > + setup_post_dividers(base, params); > + > /* Lock */ > if (lock) > do_lock_dpll(base); > > -setup_post_dividers: > - setup_post_dividers(base, params); > - > /* Wait till the DPLL locks */ > if (lock) > wait_for_lock(base); > LGTM Reviewed-by: Nishanth Menon <nm@ti.com>
On Mon, May 23, 2016 at 01:31:19PM +0530, Lokesh Vutla wrote: > All the output clock parameters of a DPLL needs to be programmed before > locking the DPLL. But it is being configured after locking the DPLL which > could potentially bypass DPLL. So fixing this sequence. > > Reported-by: Richard Woodruff <r-woodruff2@ti.com> > Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> > Reviewed-by: Nishanth Menon <nm@ti.com> Applied to u-boot/master, thanks!
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index ef2ac98..2de9935 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -236,6 +236,8 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params, /* Dpll locked with ideal values for nominal opps. */ debug("\n %s Dpll already locked with ideal" "nominal opp values", dpll); + + bypass_dpll(base); goto setup_post_dividers; } } @@ -251,13 +253,13 @@ static void do_setup_dpll(u32 const base, const struct dpll_params *params, writel(temp, &dpll_regs->cm_clksel_dpll); +setup_post_dividers: + setup_post_dividers(base, params); + /* Lock */ if (lock) do_lock_dpll(base); -setup_post_dividers: - setup_post_dividers(base, params); - /* Wait till the DPLL locks */ if (lock) wait_for_lock(base);
All the output clock parameters of a DPLL needs to be programmed before locking the DPLL. But it is being configured after locking the DPLL which could potentially bypass DPLL. So fixing this sequence. Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-)