| Message ID | 1463558049-26158-3-git-send-email-van.freenix@gmail.com |
|---|---|
| State | Changes Requested |
| Delegated to: | Stefano Babic |
| Headers | show |
Dear Peng Fan, On Wed, May 18, 2016 at 9:53 AM, Peng Fan <van.freenix@gmail.com> wrote: > Use simpler runtime cpu dection macros. > > Signed-off-by: Peng Fan <van.freenix@gmail.com> > Cc: Stefano Babic <sbabic@denx.de> > Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com> > Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> > Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com> > --- > arch/arm/imx-common/hab.c | 43 +++++++++++++----------------------------- > arch/arm/imx-common/init.c | 5 ++--- > arch/arm/imx-common/iomux-v3.c | 2 +- > arch/arm/imx-common/sata.c | 2 +- > arch/arm/imx-common/timer.c | 11 +++-------- > 5 files changed, 20 insertions(+), 43 deletions(-) > > diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c > index 8bbcc22..a980688 100644 > --- a/arch/arm/imx-common/hab.c > +++ b/arch/arm/imx-common/hab.c > @@ -17,60 +17,45 @@ > > #define hab_rvt_report_event_p \ > ( \ > - ((is_cpu_type(MXC_CPU_MX6Q) || \ > - is_cpu_type(MXC_CPU_MX6D)) && \ > - (soc_rev() >= CHIP_REV_1_5)) ? \ > + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ > ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ > - (is_cpu_type(MXC_CPU_MX6DL) && \ > - (soc_rev() >= CHIP_REV_1_2)) ? \ > + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ This change silently introduces the possibility of MXC_CPU_MX6SOLO. Is this on purpose? If so, then it means that there was something unrelated to this patch that was wrong in this code for MXC_CPU_MX6SOLO, so this should be fixed in a separate patch before this one. If not, then an is_mx6dl() macro should be introduced. > ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ > ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \ > ) > > #define hab_rvt_report_status_p \ > ( \ > - ((is_cpu_type(MXC_CPU_MX6Q) || \ > - is_cpu_type(MXC_CPU_MX6D)) && \ > - (soc_rev() >= CHIP_REV_1_5)) ? \ > + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ > ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\ > - (is_cpu_type(MXC_CPU_MX6DL) && \ > - (soc_rev() >= CHIP_REV_1_2)) ? \ > + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ Ditto. > ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\ > ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \ > ) > > #define hab_rvt_authenticate_image_p \ > ( \ > - ((is_cpu_type(MXC_CPU_MX6Q) || \ > - is_cpu_type(MXC_CPU_MX6D)) && \ > - (soc_rev() >= CHIP_REV_1_5)) ? \ > + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ > ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \ > - (is_cpu_type(MXC_CPU_MX6DL) && \ > - (soc_rev() >= CHIP_REV_1_2)) ? \ > + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ Ditto. > ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \ > ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \ > ) > > #define hab_rvt_entry_p \ > ( \ > - ((is_cpu_type(MXC_CPU_MX6Q) || \ > - is_cpu_type(MXC_CPU_MX6D)) && \ > - (soc_rev() >= CHIP_REV_1_5)) ? \ > + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ > ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \ > - (is_cpu_type(MXC_CPU_MX6DL) && \ > - (soc_rev() >= CHIP_REV_1_2)) ? \ > + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ Ditto. > ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \ > ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \ > ) > > #define hab_rvt_exit_p \ > ( \ > - ((is_cpu_type(MXC_CPU_MX6Q) || \ > - is_cpu_type(MXC_CPU_MX6D)) && \ > - (soc_rev() >= CHIP_REV_1_5)) ? \ > + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ > ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \ > - (is_cpu_type(MXC_CPU_MX6DL) && \ > - (soc_rev() >= CHIP_REV_1_2)) ? \ > + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ Ditto. > ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \ > ((hab_rvt_exit_t *)HAB_RVT_EXIT) \ > ) > @@ -424,8 +409,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size) > */ > /* Check MMU enabled */ > if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) { > - if (is_cpu_type(MXC_CPU_MX6Q) || > - is_cpu_type(MXC_CPU_MX6D)) { > + if (is_mx6dq()) { > /* > * This won't work on Rev 1.0.0 of > * i.MX6Q/D, since their ROM doesn't > @@ -434,10 +418,9 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size) > */ > if (!is_mx6dqp()) > writel(1, MX6DQ_PU_IROM_MMU_EN_VAR); > - } else if (is_cpu_type(MXC_CPU_MX6DL) || > - is_cpu_type(MXC_CPU_MX6SOLO)) { > + } else if (is_mx6sdl()) { > writel(1, MX6DLS_PU_IROM_MMU_EN_VAR); > - } else if (is_cpu_type(MXC_CPU_MX6SL)) { > + } else if (is_mx6sl()) { > writel(1, MX6SL_PU_IROM_MMU_EN_VAR); > } > } > diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c > index 15dab1d..3d2ce3a 100644 > --- a/arch/arm/imx-common/init.c > +++ b/arch/arm/imx-common/init.c > @@ -44,7 +44,7 @@ void init_aips(void) > writel(0x00000000, &aips2->opacr3); > writel(0x00000000, &aips2->opacr4); > > - if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) { > + if (is_mx6sx() || is_mx7()) { > /* > * Set all MPROTx to be non-bufferable, trusted for R/W, > * not forced to user-mode. > @@ -78,8 +78,7 @@ void imx_set_wdog_powerdown(bool enable) > writew(enable, &wdog1->wmcr); > writew(enable, &wdog2->wmcr); > > - if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || > - is_soc_type(MXC_SOC_MX7)) > + if (is_mx6sx() || is_mx6ul() || is_mx7()) > writew(enable, &wdog3->wmcr); > #ifdef CONFIG_MX7D > writew(enable, &wdog4->wmcr); > diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c > index 228d5f8..66137d1 100644 > --- a/arch/arm/imx-common/iomux-v3.c > +++ b/arch/arm/imx-common/iomux-v3.c > @@ -83,7 +83,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, > > #if defined(CONFIG_MX6QDL) > stride = 2; > - if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) > + if (!is_mx6dq()) > p += 1; > #else > stride = 1; > diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c > index d174a46..dd9698d 100644 > --- a/arch/arm/imx-common/sata.c > +++ b/arch/arm/imx-common/sata.c > @@ -15,7 +15,7 @@ int setup_sata(void) > struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; > int ret; > > - if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) > + if (!is_mx6dq()) > return 1; > > ret = enable_sata_clock(); > diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c > index 92c7218..bea17f2 100644 > --- a/arch/arm/imx-common/timer.c > +++ b/arch/arm/imx-common/timer.c > @@ -43,10 +43,8 @@ DECLARE_GLOBAL_DATA_PTR; > static inline int gpt_has_clk_source_osc(void) > { > #if defined(CONFIG_MX6) > - if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) && > - (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) || > - is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) || > - is_cpu_type(MXC_CPU_MX6UL)) > + if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || The extra parentheses around is_mx6dq() can be removed. > + is_mx6sdl() || is_mx6sx() || is_mx6ul()) > return 1; > > return 0; > @@ -86,10 +84,7 @@ int timer_init(void) > i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; > > /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */ > - if (is_cpu_type(MXC_CPU_MX6DL) || > - is_cpu_type(MXC_CPU_MX6SOLO) || > - is_cpu_type(MXC_CPU_MX6SX) || > - is_cpu_type(MXC_CPU_MX6UL)) { > + if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) { > i |= GPTCR_24MEN; > > /* Produce 3Mhz clock */ > -- > 2.6.2 Best regards, Benoît
Hi Benoît, On Fri, May 20, 2016 at 01:02:10AM +0200, Benoît Thébaudeau wrote: >Dear Peng Fan, > >On Wed, May 18, 2016 at 9:53 AM, Peng Fan <van.freenix@gmail.com> wrote: >> Use simpler runtime cpu dection macros. >> >> Signed-off-by: Peng Fan <van.freenix@gmail.com> >> Cc: Stefano Babic <sbabic@denx.de> >> Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com> >> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> >> Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com> >> --- >> arch/arm/imx-common/hab.c | 43 +++++++++++++----------------------------- >> arch/arm/imx-common/init.c | 5 ++--- >> arch/arm/imx-common/iomux-v3.c | 2 +- >> arch/arm/imx-common/sata.c | 2 +- >> arch/arm/imx-common/timer.c | 11 +++-------- >> 5 files changed, 20 insertions(+), 43 deletions(-) >> >> diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c >> index 8bbcc22..a980688 100644 >> --- a/arch/arm/imx-common/hab.c >> +++ b/arch/arm/imx-common/hab.c >> @@ -17,60 +17,45 @@ >> >> #define hab_rvt_report_event_p \ >> ( \ >> - ((is_cpu_type(MXC_CPU_MX6Q) || \ >> - is_cpu_type(MXC_CPU_MX6D)) && \ >> - (soc_rev() >= CHIP_REV_1_5)) ? \ >> + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ >> ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ >> - (is_cpu_type(MXC_CPU_MX6DL) && \ >> - (soc_rev() >= CHIP_REV_1_2)) ? \ >> + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ > >This change silently introduces the possibility of MXC_CPU_MX6SOLO. Is >this on purpose? If so, then it means that there was something Yeah. on purpose. >unrelated to this patch that was wrong in this code for >MXC_CPU_MX6SOLO, so this should be fixed in a separate patch before >this one. If not, then an is_mx6dl() macro should be introduced. 6solo and 6dl works the same. I do not plan to add a is_mx6dl here. I can refine the commit log to note this in V2. Stefano, do you have any comments on this? Thanks, Peng.
Hi Peng, On Fri, May 20, 2016 at 10:41 AM, Peng Fan <van.freenix@gmail.com> wrote: > On Fri, May 20, 2016 at 01:02:10AM +0200, Benoît Thébaudeau wrote: >>On Wed, May 18, 2016 at 9:53 AM, Peng Fan <van.freenix@gmail.com> wrote: >>> Use simpler runtime cpu dection macros. >>> >>> Signed-off-by: Peng Fan <van.freenix@gmail.com> >>> Cc: Stefano Babic <sbabic@denx.de> >>> Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com> >>> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> >>> Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com> >>> --- >>> arch/arm/imx-common/hab.c | 43 +++++++++++++----------------------------- >>> arch/arm/imx-common/init.c | 5 ++--- >>> arch/arm/imx-common/iomux-v3.c | 2 +- >>> arch/arm/imx-common/sata.c | 2 +- >>> arch/arm/imx-common/timer.c | 11 +++-------- >>> 5 files changed, 20 insertions(+), 43 deletions(-) >>> >>> diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c >>> index 8bbcc22..a980688 100644 >>> --- a/arch/arm/imx-common/hab.c >>> +++ b/arch/arm/imx-common/hab.c >>> @@ -17,60 +17,45 @@ >>> >>> #define hab_rvt_report_event_p \ >>> ( \ >>> - ((is_cpu_type(MXC_CPU_MX6Q) || \ >>> - is_cpu_type(MXC_CPU_MX6D)) && \ >>> - (soc_rev() >= CHIP_REV_1_5)) ? \ >>> + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ >>> ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ >>> - (is_cpu_type(MXC_CPU_MX6DL) && \ >>> - (soc_rev() >= CHIP_REV_1_2)) ? \ >>> + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ >> >>This change silently introduces the possibility of MXC_CPU_MX6SOLO. Is >>this on purpose? If so, then it means that there was something > > Yeah. on purpose. > >>unrelated to this patch that was wrong in this code for >>MXC_CPU_MX6SOLO, so this should be fixed in a separate patch before >>this one. If not, then an is_mx6dl() macro should be introduced. > > 6solo and 6dl works the same. I do not plan to add a is_mx6dl here. > I can refine the commit log to note this in V2. Then you can indeed either mention this in the commit message, or add a patch fixing 6solo support before this one. Best regards, Benoît
diff --git a/arch/arm/imx-common/hab.c b/arch/arm/imx-common/hab.c index 8bbcc22..a980688 100644 --- a/arch/arm/imx-common/hab.c +++ b/arch/arm/imx-common/hab.c @@ -17,60 +17,45 @@ #define hab_rvt_report_event_p \ ( \ - ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ - (is_cpu_type(MXC_CPU_MX6DL) && \ - (soc_rev() >= CHIP_REV_1_2)) ? \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT_NEW) : \ ((hab_rvt_report_event_t *)HAB_RVT_REPORT_EVENT) \ ) #define hab_rvt_report_status_p \ ( \ - ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\ - (is_cpu_type(MXC_CPU_MX6DL) && \ - (soc_rev() >= CHIP_REV_1_2)) ? \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS_NEW) :\ ((hab_rvt_report_status_t *)HAB_RVT_REPORT_STATUS) \ ) #define hab_rvt_authenticate_image_p \ ( \ - ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \ - (is_cpu_type(MXC_CPU_MX6DL) && \ - (soc_rev() >= CHIP_REV_1_2)) ? \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE_NEW) : \ ((hab_rvt_authenticate_image_t *)HAB_RVT_AUTHENTICATE_IMAGE) \ ) #define hab_rvt_entry_p \ ( \ - ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \ - (is_cpu_type(MXC_CPU_MX6DL) && \ - (soc_rev() >= CHIP_REV_1_2)) ? \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ ((hab_rvt_entry_t *)HAB_RVT_ENTRY_NEW) : \ ((hab_rvt_entry_t *)HAB_RVT_ENTRY) \ ) #define hab_rvt_exit_p \ ( \ - ((is_cpu_type(MXC_CPU_MX6Q) || \ - is_cpu_type(MXC_CPU_MX6D)) && \ - (soc_rev() >= CHIP_REV_1_5)) ? \ + (is_mx6dq() && (soc_rev() >= CHIP_REV_1_5)) ? \ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \ - (is_cpu_type(MXC_CPU_MX6DL) && \ - (soc_rev() >= CHIP_REV_1_2)) ? \ + (is_mx6sdl() && (soc_rev() >= CHIP_REV_1_2)) ? \ ((hab_rvt_exit_t *)HAB_RVT_EXIT_NEW) : \ ((hab_rvt_exit_t *)HAB_RVT_EXIT) \ ) @@ -424,8 +409,7 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size) */ /* Check MMU enabled */ if (is_soc_type(MXC_SOC_MX6) && get_cr() & CR_M) { - if (is_cpu_type(MXC_CPU_MX6Q) || - is_cpu_type(MXC_CPU_MX6D)) { + if (is_mx6dq()) { /* * This won't work on Rev 1.0.0 of * i.MX6Q/D, since their ROM doesn't @@ -434,10 +418,9 @@ uint32_t authenticate_image(uint32_t ddr_start, uint32_t image_size) */ if (!is_mx6dqp()) writel(1, MX6DQ_PU_IROM_MMU_EN_VAR); - } else if (is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO)) { + } else if (is_mx6sdl()) { writel(1, MX6DLS_PU_IROM_MMU_EN_VAR); - } else if (is_cpu_type(MXC_CPU_MX6SL)) { + } else if (is_mx6sl()) { writel(1, MX6SL_PU_IROM_MMU_EN_VAR); } } diff --git a/arch/arm/imx-common/init.c b/arch/arm/imx-common/init.c index 15dab1d..3d2ce3a 100644 --- a/arch/arm/imx-common/init.c +++ b/arch/arm/imx-common/init.c @@ -44,7 +44,7 @@ void init_aips(void) writel(0x00000000, &aips2->opacr3); writel(0x00000000, &aips2->opacr4); - if (is_cpu_type(MXC_CPU_MX6SX) || is_soc_type(MXC_SOC_MX7)) { + if (is_mx6sx() || is_mx7()) { /* * Set all MPROTx to be non-bufferable, trusted for R/W, * not forced to user-mode. @@ -78,8 +78,7 @@ void imx_set_wdog_powerdown(bool enable) writew(enable, &wdog1->wmcr); writew(enable, &wdog2->wmcr); - if (is_cpu_type(MXC_CPU_MX6SX) || is_cpu_type(MXC_CPU_MX6UL) || - is_soc_type(MXC_SOC_MX7)) + if (is_mx6sx() || is_mx6ul() || is_mx7()) writew(enable, &wdog3->wmcr); #ifdef CONFIG_MX7D writew(enable, &wdog4->wmcr); diff --git a/arch/arm/imx-common/iomux-v3.c b/arch/arm/imx-common/iomux-v3.c index 228d5f8..66137d1 100644 --- a/arch/arm/imx-common/iomux-v3.c +++ b/arch/arm/imx-common/iomux-v3.c @@ -83,7 +83,7 @@ void imx_iomux_v3_setup_multiple_pads(iomux_v3_cfg_t const *pad_list, #if defined(CONFIG_MX6QDL) stride = 2; - if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + if (!is_mx6dq()) p += 1; #else stride = 1; diff --git a/arch/arm/imx-common/sata.c b/arch/arm/imx-common/sata.c index d174a46..dd9698d 100644 --- a/arch/arm/imx-common/sata.c +++ b/arch/arm/imx-common/sata.c @@ -15,7 +15,7 @@ int setup_sata(void) struct iomuxc *const iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; int ret; - if (!is_cpu_type(MXC_CPU_MX6Q) && !is_cpu_type(MXC_CPU_MX6D)) + if (!is_mx6dq()) return 1; ret = enable_sata_clock(); diff --git a/arch/arm/imx-common/timer.c b/arch/arm/imx-common/timer.c index 92c7218..bea17f2 100644 --- a/arch/arm/imx-common/timer.c +++ b/arch/arm/imx-common/timer.c @@ -43,10 +43,8 @@ DECLARE_GLOBAL_DATA_PTR; static inline int gpt_has_clk_source_osc(void) { #if defined(CONFIG_MX6) - if (((is_cpu_type(MXC_CPU_MX6Q) || is_cpu_type(MXC_CPU_MX6D)) && - (soc_rev() > CHIP_REV_1_0)) || is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO) || is_cpu_type(MXC_CPU_MX6SX) || - is_cpu_type(MXC_CPU_MX6UL)) + if (((is_mx6dq()) && (soc_rev() > CHIP_REV_1_0)) || + is_mx6sdl() || is_mx6sx() || is_mx6ul()) return 1; return 0; @@ -86,10 +84,7 @@ int timer_init(void) i |= GPTCR_CLKSOURCE_OSC | GPTCR_TEN; /* For DL/S, SX, UL, set 24Mhz OSC Enable bit and prescaler */ - if (is_cpu_type(MXC_CPU_MX6DL) || - is_cpu_type(MXC_CPU_MX6SOLO) || - is_cpu_type(MXC_CPU_MX6SX) || - is_cpu_type(MXC_CPU_MX6UL)) { + if (is_mx6sdl() || is_mx6sx() || is_mx6ul()) { i |= GPTCR_24MEN; /* Produce 3Mhz clock */
Use simpler runtime cpu dection macros. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Stefano Babic <sbabic@denx.de> Cc: Ulises Cardenas <Ulises.Cardenas@freescale.com> Cc: Bhuvanchandra DV <bhuvanchandra.dv@toradex.com> Cc: "Benoît Thébaudeau" <benoit.thebaudeau.dev@gmail.com> --- arch/arm/imx-common/hab.c | 43 +++++++++++++----------------------------- arch/arm/imx-common/init.c | 5 ++--- arch/arm/imx-common/iomux-v3.c | 2 +- arch/arm/imx-common/sata.c | 2 +- arch/arm/imx-common/timer.c | 11 +++-------- 5 files changed, 20 insertions(+), 43 deletions(-)