From patchwork Fri Aug 20 18:37:49 2010
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Subject: [i386] : Remove ashift RSP splitter.
From: Uros Bizjak <ubizjak@gmail.com>
X-Patchwork-Id: 62302
Message-Id: <AANLkTikDJGJUXzrz_wdUd_VPr1QWB=_hEB8FHSnzHCnG@mail.gmail.com>
To: gcc-patches@gcc.gnu.org
Date: Fri, 20 Aug 2010 20:37:49 +0200

Hello!

There is no way to generate shift pattern with %rX and %rsp as
operands 0 and 1, so remove unneeded splitter. %rsp is prevented by
"index_register_operand" operand predicate as well as "l" operand
constraint in relevant insn patterns.

The patch also removes long overdue comment. We do have "incb %ah"
patterns (and more), see "*addqi_ext_..." family of patterns.

2010-08-20  Uros Bizjak  <ubizjak@gmail.com>

	* config/i386/i386.md (ashift RSP splitter): Remove splitter.
	(pro_epilogue_adjust_stack_di_2): Use "l" constraint for
	alternative 1 of operand 2.

Patch was bootstrapped on x86_64-pc-linux-gnu {,-m32}. Committed to
mainline SVN.

Uros,


Index: i386.md
===================================================================
--- i386.md	(revision 163410)
+++ i386.md	(working copy)
@@ -5935,10 +5935,6 @@
 	(const_string "*")))
    (set_attr "mode" "HI")])
 
-;; %%% After Dave's SUBREG_BYTE stuff goes in, re-enable incb %ah
-;; type optimizations enabled by define-splits.  This is not important
-;; for PII, and in fact harmful because of partial register stalls.
-
 (define_insn "*addhi_1_lea"
   [(set (match_operand:HI 0 "nonimmediate_operand" "=r,rm,r,r")
 	(plus:HI (match_operand:HI 1 "nonimmediate_operand" "%0,0,r,r")
@@ -9637,26 +9633,6 @@
   operands[2] = gen_int_mode (1 << INTVAL (operands[2]), DImode);
 })
 
-;; Rare case of shifting RSP is handled by generating move and shift
-(define_split
-  [(set (match_operand 0 "register_operand" "")
-	(ashift (match_operand 1 "register_operand" "")
-                (match_operand:QI 2 "const_int_operand" "")))
-   (clobber (reg:CC FLAGS_REG))]
-  "reload_completed
-   && true_regnum (operands[0]) != true_regnum (operands[1])"
-  [(const_int 0)]
-{
-  rtx pat, clob;
-  emit_move_insn (operands[0], operands[1]);
-  pat = gen_rtx_SET (VOIDmode, operands[0],
-		     gen_rtx_ASHIFT (GET_MODE (operands[0]),
-				     operands[0], operands[2]));
-  clob = gen_rtx_CLOBBER (VOIDmode, gen_rtx_REG (CCmode, FLAGS_REG));
-  emit_insn (gen_rtx_PARALLEL (VOIDmode, gen_rtvec (2, pat, clob)));
-  DONE;
-})
-
 ;; This pattern can't accept a variable shift count, since shifts by
 ;; zero don't affect the flags.  We assume that shifts by constant
 ;; zero are optimized away.
@@ -16411,7 +16387,7 @@
   [(set (match_operand:DI 0 "register_operand" "=r,r")
 	(plus:DI (match_operand:DI 1 "register_operand" "0,r")
 		 (match_operand:DI 3 "immediate_operand" "i,i")))
-   (use (match_operand:DI 2 "register_operand" "r,r"))
+   (use (match_operand:DI 2 "register_operand" "r,l"))
    (clobber (reg:CC FLAGS_REG))
    (clobber (mem:BLK (scratch)))]
   "TARGET_64BIT"