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[testsuite] : Hancle AVX in gcc.dg/vect/tree-vect.h

Message ID CAFULd4ZVBoAf2_dA_2i39gnAhb1Gki+GOeE6uiAF5joiceLHWg@mail.gmail.com
State New
Headers show

Commit Message

Uros Bizjak May 13, 2016, 5:29 p.m. UTC 
Also remove unneeded XOP handling.

2016-05-13  Uros Bizjak  <ubizjak@gmail.com>

    * gcc.dg/vect/tree-vect.h (check_vect): Handle AVX2,
    remove XOP handling.

Tested on x86_64-linux-gnu AVX target and committed to mainline SVN.

Patch will be backported to other release branches.

Uros.
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Patch

Index: gcc.dg/vect/tree-vect.h
===================================================================
--- gcc.dg/vect/tree-vect.h	(revision 236210)
+++ gcc.dg/vect/tree-vect.h	(working copy)
@@ -32,25 +32,26 @@  check_vect (void)
   asm volatile (".long 0x10000484");
 #elif defined(__i386__) || defined(__x86_64__)
   {
-    unsigned int a, b, c, d, want_level, want_c, want_d;
+    unsigned int a, b, c, d,
+      want_level, want_b = 0, want_c = 0, want_d = 0;
 
     /* Determine what instruction set we've been compiled for, and detect
        that we're running with it.  This allows us to at least do a compile
        check for, e.g. SSE4.1 when the machine only supports SSE2.  */
-# ifdef __XOP__
-    want_level = 0x80000001, want_c = bit_XOP, want_d = 0;
+#if defined(__AVX2__)
+    want_level = 7, want_b = bit_AVX2;
 # elif defined(__AVX__)
-    want_level = 1, want_c = bit_AVX, want_d = 0;
+    want_level = 1, want_c = bit_AVX;
 # elif defined(__SSE4_1__)
-    want_level = 1, want_c = bit_SSE4_1, want_d = 0;
+    want_level = 1, want_c = bit_SSE4_1;
 # elif defined(__SSSE3__)
-    want_level = 1, want_c = bit_SSSE3, want_d = 0;
+    want_level = 1, want_c = bit_SSSE3;
 # else
-    want_level = 1, want_c = 0, want_d = bit_SSE2;
+    want_level = 1, want_d = bit_SSE2;
 # endif
 
     if (!__get_cpuid (want_level, &a, &b, &c, &d)
-	|| ((c & want_c) | (d & want_d)) == 0)
+	|| ((b & want_b) | (c & want_c) | (d & want_d)) == 0)
       exit (0);
   }
 #elif defined(__sparc__)