@@ -435,8 +435,17 @@ static int bfin_rtc_resume(struct platform_device *pdev)
+ * Since only some of the RTC bits are maintained externally in the
+ * Vbat domain, we need to wait for the RTC MMRs to be synced into
+ * the core after waking up. This happens every RTC 1HZ. Once that
+ * has happened, we can go ahead and re-enable the important write
+ * complete interrupt event.
+ while (!(bfin_read_RTC_ISTAT() & RTC_ISTAT_SEC))