diff mbox

[RS6000] Fix ICE caused by rs6000_savres_strategy thinko

Message ID 20160503113225.GI18915@bubble.grove.modra.org
State New
Headers show

Commit Message

Alan Modra May 3, 2016, 11:32 a.m. UTC 
rev 235672 (git cffc0b35) changed the condition for SAVE_MULTIPLE/
STORE_MULTIPLE, wrongly allowing a single reg.  Bootstrapped and
regression tested powerpc64-linux.  OK to apply?

Incidentally, the added testcase function shows a regression in -m32
-Os code quality that I'll fix sometime soon.

gcc/
	* config/rs6000/rs6000.c (rs6000_savres_strategy): Correct condition
	for SAVE_MULTIPLE/STORE_MULTIPLE.
gcc/testsuite/
	* gcc.target/powerpc/savres.c: Add func using a single gpr.

Comments

Segher Boessenkool May 3, 2016, 12:03 p.m. UTC | #1 
On Tue, May 03, 2016 at 09:02:26PM +0930, Alan Modra wrote:
> rev 235672 (git cffc0b35) changed the condition for SAVE_MULTIPLE/
> STORE_MULTIPLE, wrongly allowing a single reg.  Bootstrapped and
> regression tested powerpc64-linux.  OK to apply?

Yes, this is okay for trunk, thanks for fixing it.

> Incidentally, the added testcase function shows a regression in -m32
> -Os code quality that I'll fix sometime soon.

Could you tell more please?


Segher
Alan Modra May 3, 2016, 12:09 p.m. UTC | #2 
On Tue, May 03, 2016 at 07:03:45AM -0500, Segher Boessenkool wrote:
> On Tue, May 03, 2016 at 09:02:26PM +0930, Alan Modra wrote:
> > Incidentally, the added testcase function shows a regression in -m32
> > -Os code quality that I'll fix sometime soon.
> 
> Could you tell more please?

This
000012dc <s_r31>:
    12dc:       94 21 ff b0     stwu    r1,-80(r1)
    12e0:       7c 08 02 a6     mflr    r0
    12e4:       93 e1 00 4c     stw     r31,76(r1)
    12e8:       90 01 00 54     stw     r0,84(r1)
    12ec:       3b e0 00 00     li      r31,0
    12f0:       39 61 00 50     addi    r11,r1,80
    12f4:       48 00 00 00     b       12f4 <s_r31+0x18>
                        12f4: R_PPC_REL24       _restgpr_31_x

vs. this from gcc-4.4.7
0000036c <s_r31>:
 36c:   94 21 ff c0     stwu    r1,-64(r1)
 370:   93 e1 00 3c     stw     r31,60(r1)
 374:   3b e0 00 00     li      r31,0
 378:   83 e1 00 3c     lwz     r31,60(r1)
 37c:   38 21 00 40     addi    r1,r1,64
 380:   4e 80 00 20     blr
diff mbox

Patch

diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c
index e94aa66..6fa8a0c 100644
--- a/gcc/config/rs6000/rs6000.c
+++ b/gcc/config/rs6000/rs6000.c
@@ -23438,7 +23438,7 @@  rs6000_savres_strategy (rs6000_stack_t *info,
   if (TARGET_MULTIPLE
       && !TARGET_POWERPC64
       && !(TARGET_SPE_ABI && info->spe_64bit_regs_used)
-      && info->first_gp_reg_save != 32)
+      && info->first_gp_reg_save < 31)
     {
       /* Prefer store multiple for saves over out-of-line routines,
 	 since the store-multiple instruction will always be smaller.  */
diff --git a/gcc/testsuite/gcc.target/powerpc/savres.c b/gcc/testsuite/gcc.target/powerpc/savres.c
index 5ebadf6..9432ed7 100644
--- a/gcc/testsuite/gcc.target/powerpc/savres.c
+++ b/gcc/testsuite/gcc.target/powerpc/savres.c
@@ -447,6 +447,16 @@  void s_r (void)
   __asm __volatile ("#%0" : "=m" (a) : : "r30", "r31");
 }
 
+void s_r31 (void)
+{
+  char a[33];
+#ifndef NO_BODY
+  TRASH_GPR (r31);
+  __asm__ __volatile__ ("#%0" : : "r" (r31));
+#endif
+  __asm __volatile ("#%0" : "=m" (a) : : "r31");
+}
+
 void s_c (void)
 {
   char a[33];
@@ -1154,6 +1164,8 @@  main (void)
   VERIFY_REGS;
   s_r ();
   VERIFY_REGS;
+  s_r31 ();
+  VERIFY_REGS;
   s_c ();
   VERIFY_REGS;
   s_0 ();