[i386] : Fix vector moves with const_m1 operand

Message ID	CAFULd4ZJo8ydcYm18qV+CFqu-gOc7XAaJt_NMaBv1Ng7DRNNQA@mail.gmail.com
State	New
Headers	show Return-Path: <gcc-patches-return-426266-incoming=patchwork.ozlabs.org@gcc.gnu.org> DomainKey-Signature: a=rsa-sha1; c=nofws; d=gcc.gnu.org; h=list-id :list-unsubscribe:list-archive:list-post:list-help:sender :mime-version:date:message-id:subject:from:to:content-type; q= dns; s=default; b=R9C1Ap1XIRiHkUiu4yaUoSR+KcyDSH+JFAZLrCbBpujl9e NHw6YoGvg9GAh1EXlRC0m3m8rf5xF0l8P1yR1lmYZKlcrU0NHJ38D7RRblQqQSFN 1JaVHmaqO97/q/1os7Ci0UaTbneofuuqVGvJzlWkq70ffoEFeaaBfNmzxbRFE= Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk Sender: gcc-patches-owner@gcc.gnu.org MIME-Version: 1.0 Date: Sun, 1 May 2016 21:07:37 +0200 Message-ID: <CAFULd4ZJo8ydcYm18qV+CFqu-gOc7XAaJt_NMaBv1Ng7DRNNQA@mail.gmail.com> Subject: [PATCH, i386]: Fix vector moves with const_m1 operand From: Uros Bizjak <ubizjak@gmail.com> To: "gcc-patches@gcc.gnu.org" <gcc-patches@gcc.gnu.org> Content-Type: multipart/mixed; boundary=94eb2c12355ed59e0c0531cc967b

Index: config/i386/constraints.md =================================================================== --- config/i386/constraints.md (revision 235692) +++ config/i386/constraints.md (working copy) @@ -185,10 +185,9 @@ (match_operand 0 "constant_call_address_operand")) (define_constraint "BC" - "@internal SSE constant operand." + "@internal SSE constant -1 operand." (and (match_test "TARGET_SSE") - (ior (match_test "op == const0_rtx || op == constm1_rtx") - (match_operand 0 "const0_operand") + (ior (match_test "op == constm1_rtx") (match_operand 0 "vector_all_ones_operand")))) ;; Integer constant constraints. Index: config/i386/i386.md =================================================================== --- config/i386/i386.md (revision 235692) +++ config/i386/i386.md (working copy) @@ -1970,8 +1970,8 @@ (set_attr "length_immediate" "1")]) (define_insn "*movxi_internal_avx512f" - [(set (match_operand:XI 0 "nonimmediate_operand" "=v,v ,m") - (match_operand:XI 1 "nonimmediate_or_sse_const_operand" "BC,vm,v"))] + [(set (match_operand:XI 0 "nonimmediate_operand" "=v,v ,v ,m") + (match_operand:XI 1 "nonimmediate_or_sse_const_operand" " C,BC,vm,v"))] "TARGET_AVX512F && (register_operand (operands[0], XImode) || register_operand (operands[1], XImode))" @@ -1992,13 +1992,13 @@ gcc_unreachable (); } } - [(set_attr "type" "sselog1,ssemov,ssemov") + [(set_attr "type" "sselog1,sselog1,ssemov,ssemov") (set_attr "prefix" "evex") (set_attr "mode" "XI")]) (define_insn "*movoi_internal_avx" - [(set (match_operand:OI 0 "nonimmediate_operand" "=v,v,v ,m") - (match_operand:OI 1 "nonimmediate_or_sse_const_operand" "BC,C,vm,v"))] + [(set (match_operand:OI 0 "nonimmediate_operand" "=v,v ,v ,m") + (match_operand:OI 1 "nonimmediate_or_sse_const_operand" " C,BC,vm,v"))] "TARGET_AVX && (register_operand (operands[0], OImode) || register_operand (operands[1], OImode))" @@ -2033,7 +2033,7 @@ gcc_unreachable (); } } - [(set_attr "isa" "avx2,*,*,*") + [(set_attr "isa" "*,avx2,*,*") (set_attr "type" "sselog1,sselog1,ssemov,ssemov") (set_attr "prefix" "vex") (set (attr "mode") @@ -2040,9 +2040,8 @@ (cond [(ior (match_operand 0 "ext_sse_reg_operand") (match_operand 1 "ext_sse_reg_operand")) (const_string "XI") - (and (eq_attr "alternative" "0") - (and (match_test "TARGET_AVX512VL") - (match_operand 1 "constm1_operand"))) + (and (eq_attr "alternative" "1") + (match_test "TARGET_AVX512VL")) (const_string "XI") (ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") (and (eq_attr "alternative" "3") @@ -2052,8 +2051,8 @@ (const_string "OI")))]) (define_insn "*movti_internal" - [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v ,v,v ,m") - (match_operand:TI 1 "general_operand" "riFo,re,BC,C,vm,v"))] + [(set (match_operand:TI 0 "nonimmediate_operand" "=!r ,o ,v,v ,v ,m") + (match_operand:TI 1 "general_operand" "riFo,re,C,BC,vm,v"))] "(TARGET_64BIT && !(MEM_P (operands[0]) && MEM_P (operands[1]))) || (TARGET_SSE @@ -2096,7 +2095,7 @@ gcc_unreachable (); } } - [(set_attr "isa" "x64,x64,sse2,*,*,*") + [(set_attr "isa" "x64,x64,*,sse2,*,*") (set_attr "type" "multi,multi,sselog1,sselog1,ssemov,ssemov") (set (attr "prefix") (if_then_else (eq_attr "type" "sselog1,ssemov") @@ -2108,9 +2107,8 @@ (ior (match_operand 0 "ext_sse_reg_operand") (match_operand 1 "ext_sse_reg_operand")) (const_string "XI") - (and (eq_attr "alternative" "2") - (and (match_test "TARGET_AVX512VL") - (match_operand 1 "constm1_operand"))) + (and (eq_attr "alternative" "3") + (match_test "TARGET_AVX512VL")) (const_string "XI") (ior (not (match_test "TARGET_SSE2")) (ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") Index: config/i386/sse.md =================================================================== --- config/i386/sse.md (revision 235692) +++ config/i386/sse.md (working copy) @@ -833,8 +833,10 @@ }) (define_insn "mov<mode>_internal" - [(set (match_operand:VMOVE 0 "nonimmediate_operand" "=v,v ,m") - (match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" "BC,vm,v"))] + [(set (match_operand:VMOVE 0 "nonimmediate_operand" + "=v,v ,v ,m") + (match_operand:VMOVE 1 "nonimmediate_or_sse_const_operand" + " C,BC,vm,v"))] "TARGET_SSE && (register_operand (operands[0], <MODE>mode) || register_operand (operands[1], <MODE>mode))" @@ -936,16 +938,15 @@ gcc_unreachable (); } } - [(set_attr "type" "sselog1,ssemov,ssemov") + [(set_attr "type" "sselog1,sselog1,ssemov,ssemov") (set_attr "prefix" "maybe_vex") (set (attr "mode") - (cond [(and (eq_attr "alternative" "0") - (and (match_test "TARGET_AVX512VL") - (match_operand 1 "vector_all_ones_operand"))) + (cond [(and (eq_attr "alternative" "1") + (match_test "TARGET_AVX512VL")) (const_string "XI") (and (match_test "<MODE_SIZE> == 16") (ior (match_test "TARGET_SSE_PACKED_SINGLE_INSN_OPTIMAL") - (and (eq_attr "alternative" "2") + (and (eq_attr "alternative" "3") (match_test "TARGET_SSE_TYPELESS_STORES")))) (const_string "<ssePSmode>") (match_test "TARGET_AVX") @@ -957,7 +958,16 @@ (match_test "TARGET_SSE_LOAD0_BY_PXOR")) (const_string "TI") ] - (const_string "<sseinsnmode>")))]) + (const_string "<sseinsnmode>"))) + (set (attr "enabled") + (cond [(and (match_test "<MODE_SIZE> == 16") + (eq_attr "alternative" "1")) + (symbol_ref "TARGET_SSE2") + (and (match_test "<MODE_SIZE> == 32") + (eq_attr "alternative" "1")) + (symbol_ref "TARGET_AVX2") + ] + (symbol_ref "true")))]) (define_insn "<avx512>_load<mode>_mask" [(set (match_operand:V48_AVX512VL 0 "register_operand" "=v,v") Index: testsuite/gcc.target/i386/avx256-unaligned-load-1.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-load-1.c (revision 235692) +++ testsuite/gcc.target/i386/avx256-unaligned-load-1.c (working copy) @@ -14,6 +14,6 @@ c[i] = a[i] * b[i+3]; } -/* { dg-final { scan-assembler-not "vmovups\[^\n\r]*movv8sf_internal/2" } } */ -/* { dg-final { scan-assembler "movv4sf_internal/2" } } */ +/* { dg-final { scan-assembler-not "vmovups\[^\n\r]*movv8sf_internal/3" } } */ +/* { dg-final { scan-assembler "movv4sf_internal/3" } } */ /* { dg-final { scan-assembler "vinsertf128" } } */ Index: testsuite/gcc.target/i386/avx256-unaligned-store-1.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-store-1.c (revision 235692) +++ testsuite/gcc.target/i386/avx256-unaligned-store-1.c (working copy) @@ -17,6 +17,6 @@ d[i] = c[i] * 20.0; } -/* { dg-final { scan-assembler-not "vmovups.*movv8sf_internal/3" } } */ -/* { dg-final { scan-assembler "vmovups.*movv4sf_internal/3" } } */ +/* { dg-final { scan-assembler-not "vmovups.*movv8sf_internal/4" } } */ +/* { dg-final { scan-assembler "vmovups.*movv4sf_internal/4" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ Index: testsuite/gcc.target/i386/avx256-unaligned-store-2.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-store-2.c (revision 235692) +++ testsuite/gcc.target/i386/avx256-unaligned-store-2.c (working copy) @@ -23,6 +23,6 @@ } } -/* { dg-final { scan-assembler-not "vmovups.*movv32qi_internal/3" } } */ -/* { dg-final { scan-assembler "vmovups.*movv16qi_internal/3" } } */ +/* { dg-final { scan-assembler-not "vmovups.*movv32qi_internal/4" } } */ +/* { dg-final { scan-assembler "vmovups.*movv16qi_internal/4" } } */ /* { dg-final { scan-assembler "vextract.128" } } */ Index: testsuite/gcc.target/i386/avx256-unaligned-store-3.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-store-3.c (revision 235692) +++ testsuite/gcc.target/i386/avx256-unaligned-store-3.c (working copy) @@ -17,6 +17,6 @@ d[i] = c[i] * 20.0; } -/* { dg-final { scan-assembler-not "vmovups.*movv4df_internal/3" } } */ -/* { dg-final { scan-assembler "vmovups.*movv2df_internal/3" } } */ +/* { dg-final { scan-assembler-not "vmovups.*movv4df_internal/4" } } */ +/* { dg-final { scan-assembler "vmovups.*movv2df_internal/4" } } */ /* { dg-final { scan-assembler "vextractf128" } } */ Index: testsuite/gcc.target/i386/avx256-unaligned-store-4.c =================================================================== --- testsuite/gcc.target/i386/avx256-unaligned-store-4.c (revision 235692) +++ testsuite/gcc.target/i386/avx256-unaligned-store-4.c (working copy) @@ -14,6 +14,6 @@ b[i+3] = a[i] * c[i]; } -/* { dg-final { scan-assembler "vmovups.*movv8sf_internal/3" } } */ -/* { dg-final { scan-assembler-not "movups.*movv4sf_internal/3" } } */ +/* { dg-final { scan-assembler "vmovups.*movv8sf_internal/4" } } */ +/* { dg-final { scan-assembler-not "movups.*movv4sf_internal/4" } } */ /* { dg-final { scan-assembler-not "vextractf128" } } */

[i386] : Fix vector moves with const_m1 operand

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