diff mbox

[v5,10/18] intel_iommu: Add support for PCI MSI remap

Message ID 20160428080615.GE20143@pxdev.xzpeter.org
State New
Headers show

Commit Message

Peter Xu April 28, 2016, 8:06 a.m. UTC 
On Thu, Apr 28, 2016 at 09:32:17AM +0200, Jan Kiszka wrote:
> On 2016-04-28 09:05, Peter Xu wrote:
> > This patch enables interrupt remapping for PCI devices.
> > 
> > To play the trick, one memory region "iommu_ir" is added as child region
> > of the original iommu memory region, covering range 0xfeeXXXXX (which is
> > the address range for APIC). All the writes to this range will be taken
> > as MSI, and translation is carried out only when IR is enabled.
> > 
> > Idea suggested by Paolo Bonzini.
> 
> This still lacks source (device ID) identification, right? Were did the
> memory write attribute thing go? Given that you actually introduce a
> separate MSI target address space for the IOAPIC (btw, once there will
> be more than one instance, like on real hw today) and that you will need
> yet another one for each HPET, why not address this with a common scheme
> now, ie. by transmitting the source ID along the write via that attribute?

Yes, it still lacks verification for SID. Currently there are two
ways to implement it. One is to use MemAttrs and provide
write_with_attrs() rather than write(). The other one is to keep
using write(), but instead passing in VTDAddressSpace rather than
IntelIOMMUState when init each IR memory region:

-----------------


-----------------

If to use the above method, we'll need no scheme change. But now
since MemAttrs is ready (it's ready, right?), maybe I should start
to use it, which is the standard way to do.

Thanks to point out. Will make the change in v6.

-- peterx
diff mbox

Patch

diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 7122e5b..6493093 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -2205,6 +2205,9 @@  static void vtd_mem_ir_write(void *opaque, hwaddr addr,
     int ret = 0;
     MSIMessage from = {0}, to = {0};
 
+    VTDAddressSpace *as = opaque;
+    /* Do whatever we want using as->bus and as->devfn... */
+
     from.address = (uint64_t) addr + VTD_INTERRUPT_ADDR_FIRST;
     from.data = (uint32_t) value;
 
@@ -2276,7 +2279,7 @@  VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devfn)
         memory_region_init_iommu(&vtd_dev_as->iommu, OBJECT(s),
                                  &s->iommu_ops, "intel_iommu", UINT64_MAX);
         memory_region_init_io(&vtd_dev_as->iommu_ir, OBJECT(s),
-                              &vtd_mem_ir_ops, s, "intel_iommu_ir",
+                              &vtd_mem_ir_ops, vtd_dev_as, "intel_iommu_ir",
                               VTD_INTERRUPT_ADDR_SIZE);
         memory_region_add_subregion(&vtd_dev_as->iommu, VTD_INTERRUPT_ADDR_FIRST,
                                     &vtd_dev_as->iommu_ir);