| Message ID | 1461787759-31649-11-git-send-email-d-allred@ti.com |
|---|---|
| State | Superseded |
| Delegated to: | Tom Rini |
| Headers | show |
On Wed, Apr 27, 2016 at 03:09:14PM -0500, Daniel Allred wrote: > Updated the CONFIG_SPL_TEXT_BASE to support secure parts (moving > the start address past secure reserved memory and the size of the > security certificate that precedes the boot image on secure devices). > Updated the related CONFIG_SPL_MAX_SIZE to properly reflect the > internal memory actually available on the various device flavors > (Common minimum internal RAM guaranteed for various flavors of > DRA7xx/AM57xx is 512KB). > > Signed-off-by: Daniel Allred <d-allred@ti.com> > Signed-off-by: Madan Srinivas <madans@ti.com> Successfully boot-tested on DRA74x, DRA72x, and AM572x high-security EVMs. Tested-by: Andreas Dannenberg <dannenberg@ti.com> Regards, -- Andreas Dannenberg Texas Instruments Inc
On Wed, Apr 27, 2016 at 03:09:14PM -0500, Daniel Allred wrote: > Updated the CONFIG_SPL_TEXT_BASE to support secure parts (moving > the start address past secure reserved memory and the size of the > security certificate that precedes the boot image on secure devices). > Updated the related CONFIG_SPL_MAX_SIZE to properly reflect the > internal memory actually available on the various device flavors > (Common minimum internal RAM guaranteed for various flavors of > DRA7xx/AM57xx is 512KB). > > Signed-off-by: Daniel Allred <d-allred@ti.com> > Signed-off-by: Madan Srinivas <madans@ti.com> [snip] > +/* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */ > +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) > +#define CONFIG_SPL_BOOT_END 0x4037E000 > +#else > +#define CONFIG_SPL_BOOT_END 0x4031E000 > +#endif > +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_BOOT_END - CONFIG_SPL_TEXT_BASE) TI_ROM_DL_IMAGE_AREA_END instead please, it's not something that's really configurable, at least not without a lot of reworking and thinking about how we handle this value today. Future, maybe we can move it to Kconfig
diff --git a/include/configs/ti_omap5_common.h b/include/configs/ti_omap5_common.h index b049be4..d67860c 100644 --- a/include/configs/ti_omap5_common.h +++ b/include/configs/ti_omap5_common.h @@ -130,13 +130,35 @@ /* * SPL related defines. The Public RAM memory map the ROM defines the - * area between 0x40300000 and 0x4031E000 as a download area for OMAP5 - * (dra7xx is larger, but we do not need to be larger at this time). We - * set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and + * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. + * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. + * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and * print some information. */ -#define CONFIG_SPL_TEXT_BASE 0x40300000 -#define CONFIG_SPL_MAX_SIZE (0x4031E000 - CONFIG_SPL_TEXT_BASE) +#ifdef CONFIG_TI_SECURE_DEVICE +/* + * For memory booting on HS parts, the first 4KB of the internal RAM is + * reserved for secure world use and the flash loader image is + * preceded by a secure certificate. The SPL will therefore run in internal + * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). + */ +#define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 +#define CONFIG_SPL_TEXT_BASE 0x40301350 +#else +/* + * For all booting on GP parts, the flash loader image is + * downloaded into internal RAM at address 0x40300000. + */ +#define CONFIG_SPL_TEXT_BASE 0x40300000 +#endif + +/* DRA7xx/AM57xx have 512K of SRAM, OMAP5 only 128K */ +#if defined(CONFIG_DRA7XX) || defined(CONFIG_AM57XX) +#define CONFIG_SPL_BOOT_END 0x4037E000 +#else +#define CONFIG_SPL_BOOT_END 0x4031E000 +#endif +#define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_BOOT_END - CONFIG_SPL_TEXT_BASE) #define CONFIG_SPL_DISPLAY_PRINT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \