From patchwork Tue Aug 10 07:07:39 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bryan Wu X-Patchwork-Id: 61338 X-Patchwork-Delegate: stefan.bader@canonical.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from chlorine.canonical.com (chlorine.canonical.com [91.189.94.204]) by ozlabs.org (Postfix) with ESMTP id BBE31B70F1 for ; Tue, 10 Aug 2010 17:08:19 +1000 (EST) Received: from localhost ([127.0.0.1] helo=chlorine.canonical.com) by chlorine.canonical.com with esmtp (Exim 4.69) (envelope-from ) id 1OiiwY-0003WT-S1; Tue, 10 Aug 2010 08:08:14 +0100 Received: from adelie.canonical.com ([91.189.90.139]) by chlorine.canonical.com with esmtp (Exim 4.69) (envelope-from ) id 1OiiwW-0003WB-HT for kernel-team@lists.ubuntu.com; Tue, 10 Aug 2010 08:08:12 +0100 Received: from hutte.canonical.com ([91.189.90.181]) by adelie.canonical.com with esmtp (Exim 4.69 #1 (Debian)) id 1OiiwW-0000mA-GT; Tue, 10 Aug 2010 08:08:12 +0100 Received: from [218.82.228.4] (helo=canonical.com) by hutte.canonical.com with esmtpsa (TLS-1.0:DHE_RSA_AES_128_CBC_SHA1:16) (Exim 4.69) (envelope-from ) id 1OiiwT-0002NX-5O; Tue, 10 Aug 2010 08:08:12 +0100 From: Bryan Wu To: kernel-team@lists.ubuntu.com, stefan.bader@canonical.com Subject: [PATCH] ENGR00121057 switch low power mode only support in mc13892 2.0a Date: Tue, 10 Aug 2010 15:07:39 +0800 Message-Id: <1281424059-24347-2-git-send-email-bryan.wu@canonical.com> X-Mailer: git-send-email 1.7.0.4 In-Reply-To: <1281424059-24347-1-git-send-email-bryan.wu@canonical.com> References: <1281424059-24347-1-git-send-email-bryan.wu@canonical.com> X-BeenThere: kernel-team@lists.ubuntu.com X-Mailman-Version: 2.1.9 Precedence: list List-Id: Kernel team discussions List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Sender: kernel-team-bounces@lists.ubuntu.com Errors-To: kernel-team-bounces@lists.ubuntu.com From: Shen Yong switch low power mode will cause problems on previous version of mc13892, which may break mc13892 chip. This is a fix for ENGR00120510. BugLink: http://bugs.launchpad.net/bugs/615722 Signed-off-by: Shen Yong Signed-off-by: Bryan Wu --- arch/arm/mach-mx51/mx51_babbage_pmic_mc13892.c | 30 +++++++++++++++-------- 1 files changed, 19 insertions(+), 11 deletions(-) diff --git a/arch/arm/mach-mx51/mx51_babbage_pmic_mc13892.c b/arch/arm/mach-mx51/mx51_babbage_pmic_mc13892.c index e8a03cf..13869d0 100644 --- a/arch/arm/mach-mx51/mx51_babbage_pmic_mc13892.c +++ b/arch/arm/mach-mx51/mx51_babbage_pmic_mc13892.c @@ -346,17 +346,25 @@ static int mc13892_regulator_init(struct mc13892 *mc13892) pmic_write_reg(REG_MODE_1, value, 0xffffff); /* enable switch audo mode */ - pmic_read_reg(REG_SW_4, &value, 0xffffff); - register_mask = (SWMODE_MASK << SW1MODE_LSB) | (SWMODE_MASK << SW2MODE_LSB); - value &= ~register_mask; - value |= (SWMODE_AUTO << SW1MODE_LSB) | (SWMODE_AUTO << SW2MODE_LSB); - pmic_write_reg(REG_SW_4, value, 0xffffff); - - pmic_read_reg(REG_SW_5, &value, 0xffffff); - register_mask = (SWMODE_MASK << SW3MODE_LSB) | (SWMODE_MASK << SW4MODE_LSB); - value &= ~register_mask; - value |= (SWMODE_AUTO << SW3MODE_LSB) | (SWMODE_AUTO << SW4MODE_LSB); - pmic_write_reg(REG_SW_5, value, 0xffffff); + pmic_read_reg(REG_IDENTIFICATION, &value, 0xffffff); + /* only for mc13892 2.0A */ + if ((value & 0x0000FFFF) == 0x45d0) { + pmic_read_reg(REG_SW_4, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW1MODE_LSB) | + (SWMODE_MASK << SW2MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW1MODE_LSB) | + (SWMODE_AUTO << SW2MODE_LSB); + pmic_write_reg(REG_SW_4, value, 0xffffff); + + pmic_read_reg(REG_SW_5, &value, 0xffffff); + register_mask = (SWMODE_MASK << SW3MODE_LSB) | + (SWMODE_MASK << SW4MODE_LSB); + value &= ~register_mask; + value |= (SWMODE_AUTO << SW3MODE_LSB) | + (SWMODE_AUTO << SW4MODE_LSB); + pmic_write_reg(REG_SW_5, value, 0xffffff); + } /* Enable coin cell charger */ value = BITFVAL(CIONCHEN, 1) | BITFVAL(VCOIN, VCOIN_3_0V);