From patchwork Thu Apr 21 22:27:29 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stephen Warren X-Patchwork-Id: 613336 X-Patchwork-Delegate: treding@nvidia.com Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by ozlabs.org (Postfix) with ESMTP id 3qrYKZ200Gz9sdQ for ; Fri, 22 Apr 2016 08:27:46 +1000 (AEST) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751710AbcDUW1p (ORCPT ); Thu, 21 Apr 2016 18:27:45 -0400 Received: from avon.wwwdotorg.org ([70.85.31.133]:38116 "EHLO avon.wwwdotorg.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751594AbcDUW1o (ORCPT ); Thu, 21 Apr 2016 18:27:44 -0400 Received: from swarren-lx1.nvidia.com (thunderhill.nvidia.com [216.228.112.22]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) by avon.wwwdotorg.org (Postfix) with ESMTPSA id 3B86C1C03BD; Thu, 21 Apr 2016 16:27:41 -0600 (MDT) X-Virus-Status: Clean X-Virus-Scanned: clamav-milter 0.99 at avon.wwwdotorg.org From: Stephen Warren To: Thierry Reding Cc: Alexandre Courbot , linux-tegra@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Stephen Warren Subject: [PATCH] ARM: tegra: import latest Jetson TK1 spreadsheet Date: Thu, 21 Apr 2016 16:27:29 -0600 Message-Id: <1461277649-18173-1-git-send-email-swarren@wwwdotorg.org> X-Mailer: git-send-email 2.8.1 X-NVConfidentiality: public Sender: linux-tegra-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-tegra@vger.kernel.org From: Stephen Warren This imports v11 of "Jetson TK1 Development Platform Pin Mux" from https://developer.nvidia.com/embedded/downloads. The new version defines the mux option for the MIPI pad ctrl selection. The OWR pin no longer has an entry in the configuration table because the only mux option it support is OWR, that feature isn't supported, and hence can't conflict with any other pin. This pin can only usefully be used as a GPIO. Signed-off-by: Stephen Warren --- arch/arm/boot/dts/tegra124-jetson-tk1.dts | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/arch/arm/boot/dts/tegra124-jetson-tk1.dts b/arch/arm/boot/dts/tegra124-jetson-tk1.dts index 66b4451eb2ca..f8242ee70be3 100644 --- a/arch/arm/boot/dts/tegra124-jetson-tk1.dts +++ b/arch/arm/boot/dts/tegra124-jetson-tk1.dts @@ -1342,14 +1342,6 @@ nvidia,tristate = ; nvidia,enable-input = ; }; - owr { - nvidia,pins = "owr"; - nvidia,function = "rsvd2"; - nvidia,pull = ; - nvidia,tristate = ; - nvidia,enable-input = ; - nvidia,rcv-sel = ; - }; clk_32k_in { nvidia,pins = "clk_32k_in"; nvidia,function = "clk"; @@ -1364,6 +1356,10 @@ nvidia,tristate = ; nvidia,enable-input = ; }; + dsi_b { + nvidia,pins = "mipi_pad_ctrl_dsi_b"; + nvidia,function = "dsi_b"; + }; }; };