diff mbox

[U-Boot,5/7] ARM: hisilicon: hikey: dts: Add pl011 additional clock binding.

Message ID 1461168843-15610-6-git-send-email-peter.griffin@linaro.org
State Accepted
Commit 7e4902d47933eeeadb2eb5505683ffafa96691b7
Delegated to: Tom Rini
Headers show

Commit Message

Peter Griffin April 20, 2016, 4:14 p.m. UTC 
This is a binding which only exists in U-Boot, but is
required to get working serial in U-Boot.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
---
 arch/arm/dts/hi6220.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Tom Rini April 21, 2016, 1:40 p.m. UTC | #1 
On Wed, Apr 20, 2016 at 05:14:01PM +0100, Peter Griffin wrote:

> This is a binding which only exists in U-Boot, but is
> required to get working serial in U-Boot.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>

Reviewed-by: Tom Rini <trini@konsulko.com>
Tom Rini April 26, 2016, 12:16 a.m. UTC | #2 
On Wed, Apr 20, 2016 at 05:14:01PM +0100, Peter Griffin wrote:

> This is a binding which only exists in U-Boot, but is
> required to get working serial in U-Boot.
> 
> Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Applied to u-boot/master, thanks!
diff mbox

Patch

diff --git a/arch/arm/dts/hi6220.dtsi b/arch/arm/dts/hi6220.dtsi
index ad1f1eb..a610ccb 100644
--- a/arch/arm/dts/hi6220.dtsi
+++ b/arch/arm/dts/hi6220.dtsi
@@ -166,6 +166,7 @@ 
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf8015000 0x0 0x1000>;
 			interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&ao_ctrl HI6220_UART0_PCLK>,
 				 <&ao_ctrl HI6220_UART0_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -175,6 +176,7 @@ 
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7111000 0x0 0x1000>;
 			interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART1_PCLK>,
 				 <&sys_ctrl HI6220_UART1_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -185,6 +187,7 @@ 
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7112000 0x0 0x1000>;
 			interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART2_PCLK>,
 				 <&sys_ctrl HI6220_UART2_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -195,6 +198,7 @@ 
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7113000 0x0 0x1000>;
 			interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART3_PCLK>,
 				 <&sys_ctrl HI6220_UART3_PCLK>;
 			clock-names = "uartclk", "apb_pclk";
@@ -204,6 +208,7 @@ 
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0x0 0xf7114000 0x0 0x1000>;
 			interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
+			clock = <19200000>;
 			clocks = <&sys_ctrl HI6220_UART4_PCLK>,
 				 <&sys_ctrl HI6220_UART4_PCLK>;
 			clock-names = "uartclk", "apb_pclk";