From patchwork Mon Aug 9 15:56:57 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sofiane Naci X-Patchwork-Id: 61286 Return-Path: X-Original-To: incoming@patchwork.ozlabs.org Delivered-To: patchwork-incoming@bilbo.ozlabs.org Received: from sourceware.org (server1.sourceware.org [209.132.180.131]) by ozlabs.org (Postfix) with SMTP id 0C97AB6EF1 for ; Tue, 10 Aug 2010 01:57:19 +1000 (EST) Received: (qmail 14524 invoked by alias); 9 Aug 2010 15:57:18 -0000 Received: (qmail 14305 invoked by uid 22791); 9 Aug 2010 15:57:13 -0000 X-SWARE-Spam-Status: No, hits=1.0 required=5.0 tests=BAYES_50, MIME_QP_LONG_LINE, MSGID_MULTIPLE_AT, TW_CN, TW_QH, TW_VQ, T_RP_MATCHES_RCVD X-Spam-Check-By: sourceware.org Received: from cam-admin0.cambridge.arm.com (HELO cam-admin0.cambridge.arm.com) (217.140.96.50) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 09 Aug 2010 15:57:04 +0000 Received: from cam-owa2.Emea.Arm.com (cam-owa2.emea.arm.com [10.1.105.18]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id o79FuVF9029945 for ; Mon, 9 Aug 2010 16:56:31 +0100 (BST) Received: from e102113 ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 9 Aug 2010 16:57:01 +0100 From: "Sofiane Naci" To: Subject: [Patch] Refactoring of the ARM backend iterators and attributes Date: Mon, 9 Aug 2010 16:56:57 +0100 Message-ID: <000001cb37db$7eeba8d0$7cc2fa70$@Naci@arm.com> MIME-Version: 1.0 x-cr-hashedpuzzle: AGLN AQA+ AzJe BExv Bnt6 Brvn Eo1F ExKa FNvp FWcr GIwa GJ+d Go8Z HiA6 ICbL JJIW; 1; ZwBjAGMALQBwAGEAdABjAGgAZQBzAEAAZwBjAGMALgBnAG4AdQAuAG8AcgBnAA==; Sosha1_v1; 7; {FF8C5BA6-4A5B-4D6B-BA17-C463B14499FA}; cwBvAGYAaQBhAG4AZQAuAG4AYQBjAGkAQABhAHIAbQAuAGMAbwBtAA==; Mon, 09 Aug 2010 15:56:54 GMT; WwBQAGEAdABjAGgAXQAgAFIAZQBmAGEAYwB0AG8AcgBpAG4AZwAgAG8AZgAgAHQAaABlACAAQQBSAE0AIABiAGEAYwBrAGUAbgBkACAAaQB0AGUAcgBhAHQAbwByAHMAIABhAG4AZAAgAGEAdAB0AHIAaQBiAHUAdABlAHMA x-cr-puzzleid: {FF8C5BA6-4A5B-4D6B-BA17-C463B14499FA} Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Unsubscribe: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Delivered-To: mailing list gcc-patches@gcc.gnu.org Hi, This patch factors out the code and mode iterators and attributes in the ARM backend into a separate file (iterators.md) that is then included in arm.md. This enables future updated to iterators to be implemented in a common location, independent form specific machine descriptions. Tested successfully with no regressions. Tested on the GNU testsuite on QEMU with an arm-eabi compiler configured for cortex-a8 with neon enabled. Many thanks Sofiane ----- 2010-08-09 Sofiane Naci * config/arm/iterators.md: New file. * config/arm/arm.md: include "iterators.md". (QHSI): Move to new file. (LTUGEU): Likewise. (cnb): Likewise. (optab): Likewise. (ior_xor): Likewise. * config/arm/iwmmxt.md (VMMX): Move to new file. (VSHFT): Likewise. (MMX_char): Likewise. * config/arm/neon.md (VD): Move to new file. (VDX): Likewise. (VDI): Likewise. (VQ): Likewise. (VQX): Likewise. (VQI): Likewise. (VQXMOV): Likewise. (VSTRUCT): Likewise. (VTAB): Likewise. (VTAB_n): Likewise. (VW): Likewise. (VN): Likewise. (VDQ): Likewise. (VDQW): Likewise. (VDQIW): Likewise. (VDQI): Likewise. (VDQX): Likewise. (VDQIX): Likewise. (VCVTF): Likewise. (VCVTI): Likewise. (VMD): Likewise. (VMQ): Likewise. (VMDQ): Likewise. (VMDI): Likewise. (VMQI): Likewise. (VMDQI): Likewise. (VX): Likewise. (VE): Likewise. (V64): Likewise. (V32): Likewise. (V_CVTTO): Likewise. (V_elem): Likewise. (V_ext): Likewise. (V_two_elem): Likewise. (V_three_elem): Likewise. (V_four_elem): Likewise. (V_reg): Likewise. (V_widen): Likewise. (V_narrow): Likewise. (V_HALF): Likewise. (V_half): Likewise. (V_DOUBLE): Likewise. (V_double): Likewise. (V_double_width): Likewise. (V_double_vector_mode): Likewise. (V_cmp_result): Likewise. (V_if_elem): Likewise. (V_s_elem): Likewise. (V_u_elem): Likewise. (V_uf_sclr): Likewise. (V_sz_elem): Likewise. (VD_dup): Likewise. (V_PAIR): Likewise. (V_pair): Likewise. (vqh_ops): Likewise. (vqhs_ops): Likewise. (VQH_mnem): Likewise. (VQH_sign): Likewise. (V_suf64): Likewise. (scalar_mul_constraint): Likewise. (Is_float_mode): Likewise. (Scalar_mul_8_16): Likewise. (Is_d_reg): Likewise. (V_mode_nunits): Likewise. * config/arm/vec-common.md (VALL): Move to new file. (VALLW): Likewise. (VINT): Likewise. (VINTW): Likewise. diff -rupNB -x '.svn*' baseline/trunk/source/gcc/config/arm/arm.md dev/trunk/source/gcc/config/arm/arm.md --- baseline/trunk/source/gcc/config/arm/arm.md 2010-08-05 17:43:37.090446000 +0100 +++ dev/trunk/source/gcc/config/arm/arm.md 2010-08-06 15:19:25.712714000 +0100 @@ -399,13 +399,7 @@ ;;--------------------------------------------------------------------------- ;; Mode iterators -; A list of modes that are exactly 64 bits in size. We use this to expand -; some splits that are the same for all modes when operating on ARM -; registers. -(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF]) - -;; The integer modes up to word size -(define_mode_iterator QHSI [QI HI SI]) +(include "iterators.md") ;;--------------------------------------------------------------------------- ;; Predicates @@ -866,10 +860,6 @@ [(set_attr "conds" "set")] ) -(define_code_iterator LTUGEU [ltu geu]) -(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) -(define_code_attr optab [(ltu "ltu") (geu "geu")]) - (define_insn "*addsi3_carryin_" [(set (match_operand:SI 0 "s_register_operand" "=r") (plus:SI (plus:SI (match_operand:SI 1 "s_register_operand" "%r") @@ -4258,7 +4248,6 @@ "" ) -(define_code_iterator ior_xor [ior xor]) (define_split [(set (match_operand:SI 0 "s_register_operand" "") diff -rupNB -x '.svn*' baseline/trunk/source/gcc/config/arm/iterators.md dev/trunk/source/gcc/config/arm/iterators.md --- baseline/trunk/source/gcc/config/arm/iterators.md 1970-01-01 01:00:00.000000000 +0100 +++ dev/trunk/source/gcc/config/arm/iterators.md 2010-08-06 16:04:07.430347000 +0100 @@ -0,0 +1,377 @@ +;; Code and mode itertator and attribute definitions for the ARM backend +;; Copyright (C) 2010 Free Software Foundation, Inc. +;; Contributed by ARM Ltd. +;; +;; This file is part of GCC. +;; +;; GCC is free software; you can redistribute it and/or modify it +;; under the terms of the GNU General Public License as published +;; by the Free Software Foundation; either version 3, or (at your +;; option) any later version. + +;; GCC is distributed in the hope that it will be useful, but WITHOUT +;; ANY WARRANTY; without even the implied warranty of MERCHANTABILITY +;; or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public +;; License for more details. + +;; You should have received a copy of the GNU General Public License +;; along with GCC; see the file COPYING3. If not see +;; . + + +;;---------------------------------------------------------------------------- +;; Mode iterators +;;---------------------------------------------------------------------------- + +;; A list of modes that are exactly 64 bits in size. This is used to expand +;; some splits that are the same for all modes when operating on ARM +;; registers. +(define_mode_iterator ANY64 [DI DF V8QI V4HI V2SI V2SF]) + +;; A list of integer modes that are up to one word long +(define_mode_iterator QHSI [QI HI SI]) + +;; Integer element sizes implemented by IWMMXT. +(define_mode_iterator VMMX [V2SI V4HI V8QI]) + +;; Integer element sizes for shifts. +(define_mode_iterator VSHFT [V4HI V2SI DI]) + +;; Integer and float modes supported by Neon and IWMMXT. +(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) + +;; Integer and float modes supported by Neon and IWMMXT, except V2DI. +(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) + +;; Integer modes supported by Neon and IWMMXT +(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) + +;; Integer modes supported by Neon and IWMMXT, except V2DI +(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) + +;; Double-width vector modes. +(define_mode_iterator VD [V8QI V4HI V2SI V2SF]) + +;; Double-width vector modes plus 64-bit elements. +(define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI]) + +;; Double-width vector modes without floating-point elements. +(define_mode_iterator VDI [V8QI V4HI V2SI]) + +;; Quad-width vector modes. +(define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) + +;; Quad-width vector modes plus 64-bit elements. +(define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI]) + +;; Quad-width vector modes without floating-point elements. +(define_mode_iterator VQI [V16QI V8HI V4SI]) + +;; Quad-width vector modes, with TImode added, for moves. +(define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI]) + +;; Opaque structure types wider than TImode. +(define_mode_iterator VSTRUCT [EI OI CI XI]) + +;; Opaque structure types used in table lookups (except vtbl1/vtbx1). +(define_mode_iterator VTAB [TI EI OI]) + +;; Widenable modes. +(define_mode_iterator VW [V8QI V4HI V2SI]) + +;; Narrowable modes. +(define_mode_iterator VN [V8HI V4SI V2DI]) + +;; All supported vector modes (except singleton DImode). +(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI]) + +;; All supported vector modes (except those with 64-bit integer elements). +(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) + +;; Supported integer vector modes (not 64 bit elements). +(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) + +;; Supported integer vector modes (not singleton DI) +(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) + +;; Vector modes, including 64-bit integer elements. +(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI]) + +;; Vector modes including 64-bit integer elements, but no floats. +(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) + +;; Vector modes for float->int conversions. +(define_mode_iterator VCVTF [V2SF V4SF]) + +;; Vector modes form int->float conversions. +(define_mode_iterator VCVTI [V2SI V4SI]) + +;; Vector modes for doubleword multiply-accumulate, etc. insns. +(define_mode_iterator VMD [V4HI V2SI V2SF]) + +;; Vector modes for quadword multiply-accumulate, etc. insns. +(define_mode_iterator VMQ [V8HI V4SI V4SF]) + +;; Above modes combined. +(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) + +;; As VMD, but integer modes only. +(define_mode_iterator VMDI [V4HI V2SI]) + +;; As VMQ, but integer modes only. +(define_mode_iterator VMQI [V8HI V4SI]) + +;; Above modes combined. +(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) + +;; Modes with 8-bit and 16-bit elements. +(define_mode_iterator VX [V8QI V4HI V16QI V8HI]) + +;; Modes with 8-bit elements. +(define_mode_iterator VE [V8QI V16QI]) + +;; Modes with 64-bit elements only. +(define_mode_iterator V64 [DI V2DI]) + +;; Modes with 32-bit elements only. +(define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) + + +;;---------------------------------------------------------------------------- +;; Code iterators +;;---------------------------------------------------------------------------- + +;; A list of condition codes used in compare instructions where +;; the carry flag from the addition is used instead of doing the +;; compare a second time. +(define_code_iterator LTUGEU [ltu geu]) + +;; A list of ... +(define_code_iterator ior_xor [ior xor]) + +;; Operations on two halves of a quadword vector. +(define_code_iterator vqh_ops [plus smin smax umin umax]) + +;; Operations on two halves of a quadword vector, +;; without unsigned variants (for use with *SFmode pattern). +(define_code_iterator vqhs_ops [plus smin smax]) + + +;;---------------------------------------------------------------------------- +;; Mode attributes +;;---------------------------------------------------------------------------- + +;; Determine element size suffix from vector mode. +(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) + +;; vtbl suffix for NEON vector modes. +(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) + +;; (Opposite) mode to convert to/from for NEON mode conversions. +(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") + (V4SI "V4SF") (V4SF "V4SI")]) + +;; Define element mode for each vector mode. +(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") + (V4HI "HI") (V8HI "HI") + (V2SI "SI") (V4SI "SI") + (V2SF "SF") (V4SF "SF") + (DI "DI") (V2DI "DI")]) + +;; Element modes for vector extraction, padded up to register size. + +(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") + (V4HI "SI") (V8HI "SI") + (V2SI "SI") (V4SI "SI") + (V2SF "SF") (V4SF "SF") + (DI "DI") (V2DI "DI")]) + +;; Mode of pair of elements for each vector mode, to define transfer +;; size for structure lane/dup loads and stores. +(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") + (V4HI "SI") (V8HI "SI") + (V2SI "V2SI") (V4SI "V2SI") + (V2SF "V2SF") (V4SF "V2SF") + (DI "V2DI") (V2DI "V2DI")]) + +;; Similar, for three elements. +;; ??? Should we define extra modes so that sizes of all three-element +;; accesses can be accurately represented? +(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI") + (V4HI "V4HI") (V8HI "V4HI") + (V2SI "V4SI") (V4SI "V4SI") + (V2SF "V4SF") (V4SF "V4SF") + (DI "EI") (V2DI "EI")]) + +;; Similar, for four elements. +(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") + (V4HI "V4HI") (V8HI "V4HI") + (V2SI "V4SI") (V4SI "V4SI") + (V2SF "V4SF") (V4SF "V4SF") + (DI "OI") (V2DI "OI")]) + +;; Register width from element mode +(define_mode_attr V_reg [(V8QI "P") (V16QI "q") + (V4HI "P") (V8HI "q") + (V2SI "P") (V4SI "q") + (V2SF "P") (V4SF "q") + (DI "P") (V2DI "q")]) + +;; Wider modes with the same number of elements. +(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) + +;; Narrower modes with the same number of elements. +(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) + +;; Modes with half the number of equal-sized elements. +(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") + (V4SI "V2SI") (V4SF "V2SF") + (V2DI "DI")]) + +;; Same, but lower-case. +(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") + (V4SI "v2si") (V4SF "v2sf") + (V2DI "di")]) + +;; Modes with twice the number of equal-sized elements. +(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") + (V2SI "V4SI") (V2SF "V4SF") + (DI "V2DI")]) + +;; Same, but lower-case. +(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") + (V2SI "v4si") (V2SF "v4sf") + (DI "v2di")]) + +;; Modes with double-width elements. +(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") + (V4HI "V2SI") (V8HI "V4SI") + (V2SI "DI") (V4SI "V2DI")]) + +;; Double-sized modes with the same element size. +;; Used for neon_vdup_lane, where the second operand is double-sized +;; even when the first one is quad. +(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") + (V4SI "V2SI") (V4SF "V2SF") + (V8QI "V8QI") (V4HI "V4HI") + (V2SI "V2SI") (V2SF "V2SF")]) + +;; Mode of result of comparison operations (and bit-select operand 1). +(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") + (V4HI "V4HI") (V8HI "V8HI") + (V2SI "V2SI") (V4SI "V4SI") + (V2SF "V2SI") (V4SF "V4SI") + (DI "DI") (V2DI "V2DI")]) + +;; Get element type from double-width mode, for operations where we +;; don't care about signedness. +(define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") + (V4HI "i16") (V8HI "i16") + (V2SI "i32") (V4SI "i32") + (DI "i64") (V2DI "i64") + (V2SF "f32") (V4SF "f32")]) + +;; Same, but for operations which work on signed values. +(define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") + (V4HI "s16") (V8HI "s16") + (V2SI "s32") (V4SI "s32") + (DI "s64") (V2DI "s64") + (V2SF "f32") (V4SF "f32")]) + +;; Same, but for operations which work on unsigned values. +(define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") + (V4HI "u16") (V8HI "u16") + (V2SI "u32") (V4SI "u32") + (DI "u64") (V2DI "u64") + (V2SF "f32") (V4SF "f32")]) + +;; Element types for extraction of unsigned scalars. +(define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") + (V4HI "u16") (V8HI "u16") + (V2SI "32") (V4SI "32") + (V2SF "32") (V4SF "32")]) + +(define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") + (V4HI "16") (V8HI "16") + (V2SI "32") (V4SI "32") + (DI "64") (V2DI "64") + (V2SF "32") (V4SF "32")]) + +;; Element sizes for duplicating ARM registers to all elements of a vector. +(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) + +;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) +(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") + (V4HI "TI") (V8HI "OI") + (V2SI "TI") (V4SI "OI") + (V2SF "TI") (V4SF "OI") + (DI "TI") (V2DI "OI")]) + +;; Same, but lower-case. +(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") + (V4HI "ti") (V8HI "oi") + (V2SI "ti") (V4SI "oi") + (V2SF "ti") (V4SF "oi") + (DI "ti") (V2DI "oi")]) + +;; Extra suffix on some 64-bit insn names (to avoid collision with standard +;; names which we don't want to define). +(define_mode_attr V_suf64 [(V8QI "") (V16QI "") + (V4HI "") (V8HI "") + (V2SI "") (V4SI "") + (V2SF "") (V4SF "") + (DI "_neon") (V2DI "")]) + + +;; Scalars to be presented to scalar multiplication instructions +;; must satisfy the following constraints. +;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. +;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. + +;; This mode attribute is used to obtain the correct register constraints. + +(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") + (V8HI "x") (V4SI "t") (V4SF "t")]) + +;; Predicates used for setting neon_type + +(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") + (V4HI "false") (V8HI "false") + (V2SI "false") (V4SI "false") + (V2SF "true") (V4SF "true") + (DI "false") (V2DI "false")]) + +(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") + (V4HI "true") (V8HI "true") + (V2SI "false") (V4SI "false") + (V2SF "false") (V4SF "false") + (DI "false") (V2DI "false")]) + + +(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") + (V4HI "true") (V8HI "false") + (V2SI "true") (V4SI "false") + (V2SF "true") (V4SF "false") + (DI "true") (V2DI "false")]) + +(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") + (V4HI "4") (V8HI "8") + (V2SI "2") (V4SI "4") + (V2SF "2") (V4SF "4") + (DI "1") (V2DI "2")]) + + +;;---------------------------------------------------------------------------- +;; Code attributes +;;---------------------------------------------------------------------------- + +;; Assembler mnemonics for vqh_ops and vqhs_ops iterators. +(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") + (umin "vmin") (umax "vmax")]) + +;; Signs of above, where relevant. +(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") + (umax "u")]) + +(define_code_attr cnb [(ltu "CC_C") (geu "CC")]) +(define_code_attr optab [(ltu "ltu") (geu "geu")]) diff -rupNB -x '.svn*' baseline/trunk/source/gcc/config/arm/iwmmxt.md dev/trunk/source/gcc/config/arm/iwmmxt.md --- baseline/trunk/source/gcc/config/arm/iwmmxt.md 2010-08-05 17:43:36.977440000 +0100 +++ dev/trunk/source/gcc/config/arm/iwmmxt.md 2010-08-06 15:21:29.004287000 +0100 @@ -19,14 +19,6 @@ ;; along with GCC; see the file COPYING3. If not see ;; . -;; Integer element sizes implemented by IWMMXT. -(define_mode_iterator VMMX [V2SI V4HI V8QI]) - -;; Integer element sizes for shifts. -(define_mode_iterator VSHFT [V4HI V2SI DI]) - -;; Determine element size suffix from vector mode. -(define_mode_attr MMX_char [(V8QI "b") (V4HI "h") (V2SI "w") (DI "d")]) (define_insn "iwmmxt_iordi3" [(set (match_operand:DI 0 "register_operand" "=y,?&r,?&r") diff -rupNB -x '.svn*' baseline/trunk/source/gcc/config/arm/neon.md dev/trunk/source/gcc/config/arm/neon.md --- baseline/trunk/source/gcc/config/arm/neon.md 2010-08-06 15:37:22.758370000 +0100 +++ dev/trunk/source/gcc/config/arm/neon.md 2010-08-06 15:27:39.580915000 +0100 @@ -142,304 +142,11 @@ (UNSPEC_VZIP1 203) (UNSPEC_VZIP2 204)]) -;; Double-width vector modes. -(define_mode_iterator VD [V8QI V4HI V2SI V2SF]) - -;; Double-width vector modes plus 64-bit elements. -(define_mode_iterator VDX [V8QI V4HI V2SI V2SF DI]) - -;; Same, without floating-point elements. -(define_mode_iterator VDI [V8QI V4HI V2SI]) - -;; Quad-width vector modes. -(define_mode_iterator VQ [V16QI V8HI V4SI V4SF]) - -;; Quad-width vector modes plus 64-bit elements. -(define_mode_iterator VQX [V16QI V8HI V4SI V4SF V2DI]) - -;; Same, without floating-point elements. -(define_mode_iterator VQI [V16QI V8HI V4SI]) - -;; Same, with TImode added, for moves. -(define_mode_iterator VQXMOV [V16QI V8HI V4SI V4SF V2DI TI]) - -;; Opaque structure types wider than TImode. -(define_mode_iterator VSTRUCT [EI OI CI XI]) - -;; Opaque structure types used in table lookups (except vtbl1/vtbx1). -(define_mode_iterator VTAB [TI EI OI]) - -;; vtbl suffix for above modes. -(define_mode_attr VTAB_n [(TI "2") (EI "3") (OI "4")]) - -;; Widenable modes. -(define_mode_iterator VW [V8QI V4HI V2SI]) - -;; Narrowable modes. -(define_mode_iterator VN [V8HI V4SI V2DI]) - -;; All supported vector modes (except singleton DImode). -(define_mode_iterator VDQ [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF V2DI]) - -;; All supported vector modes (except those with 64-bit integer elements). -(define_mode_iterator VDQW [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF]) - -;; Supported integer vector modes (not 64 bit elements). -(define_mode_iterator VDQIW [V8QI V16QI V4HI V8HI V2SI V4SI]) - -;; Supported integer vector modes (not singleton DI) -(define_mode_iterator VDQI [V8QI V16QI V4HI V8HI V2SI V4SI V2DI]) - -;; Vector modes, including 64-bit integer elements. -(define_mode_iterator VDQX [V8QI V16QI V4HI V8HI V2SI V4SI V2SF V4SF DI V2DI]) - -;; Vector modes including 64-bit integer elements, but no floats. -(define_mode_iterator VDQIX [V8QI V16QI V4HI V8HI V2SI V4SI DI V2DI]) - -;; Vector modes for float->int conversions. -(define_mode_iterator VCVTF [V2SF V4SF]) - -;; Vector modes form int->float conversions. -(define_mode_iterator VCVTI [V2SI V4SI]) - -;; Vector modes for doubleword multiply-accumulate, etc. insns. -(define_mode_iterator VMD [V4HI V2SI V2SF]) - -;; Vector modes for quadword multiply-accumulate, etc. insns. -(define_mode_iterator VMQ [V8HI V4SI V4SF]) - -;; Above modes combined. -(define_mode_iterator VMDQ [V4HI V2SI V2SF V8HI V4SI V4SF]) - -;; As VMD, but integer modes only. -(define_mode_iterator VMDI [V4HI V2SI]) - -;; As VMQ, but integer modes only. -(define_mode_iterator VMQI [V8HI V4SI]) - -;; Above modes combined. -(define_mode_iterator VMDQI [V4HI V2SI V8HI V4SI]) - -;; Modes with 8-bit and 16-bit elements. -(define_mode_iterator VX [V8QI V4HI V16QI V8HI]) - -;; Modes with 8-bit elements. -(define_mode_iterator VE [V8QI V16QI]) - -;; Modes with 64-bit elements only. -(define_mode_iterator V64 [DI V2DI]) - -;; Modes with 32-bit elements only. -(define_mode_iterator V32 [V2SI V2SF V4SI V4SF]) - -;; (Opposite) mode to convert to/from for above conversions. -(define_mode_attr V_CVTTO [(V2SI "V2SF") (V2SF "V2SI") - (V4SI "V4SF") (V4SF "V4SI")]) - -;; Define element mode for each vector mode. -(define_mode_attr V_elem [(V8QI "QI") (V16QI "QI") - (V4HI "HI") (V8HI "HI") - (V2SI "SI") (V4SI "SI") - (V2SF "SF") (V4SF "SF") - (DI "DI") (V2DI "DI")]) - -;; Element modes for vector extraction, padded up to register size. - -(define_mode_attr V_ext [(V8QI "SI") (V16QI "SI") - (V4HI "SI") (V8HI "SI") - (V2SI "SI") (V4SI "SI") - (V2SF "SF") (V4SF "SF") - (DI "DI") (V2DI "DI")]) - -;; Mode of pair of elements for each vector mode, to define transfer -;; size for structure lane/dup loads and stores. -(define_mode_attr V_two_elem [(V8QI "HI") (V16QI "HI") - (V4HI "SI") (V8HI "SI") - (V2SI "V2SI") (V4SI "V2SI") - (V2SF "V2SF") (V4SF "V2SF") - (DI "V2DI") (V2DI "V2DI")]) - -;; Similar, for three elements. -;; ??? Should we define extra modes so that sizes of all three-element -;; accesses can be accurately represented? -(define_mode_attr V_three_elem [(V8QI "SI") (V16QI "SI") - (V4HI "V4HI") (V8HI "V4HI") - (V2SI "V4SI") (V4SI "V4SI") - (V2SF "V4SF") (V4SF "V4SF") - (DI "EI") (V2DI "EI")]) - -;; Similar, for four elements. -(define_mode_attr V_four_elem [(V8QI "SI") (V16QI "SI") - (V4HI "V4HI") (V8HI "V4HI") - (V2SI "V4SI") (V4SI "V4SI") - (V2SF "V4SF") (V4SF "V4SF") - (DI "OI") (V2DI "OI")]) - -;; Register width from element mode -(define_mode_attr V_reg [(V8QI "P") (V16QI "q") - (V4HI "P") (V8HI "q") - (V2SI "P") (V4SI "q") - (V2SF "P") (V4SF "q") - (DI "P") (V2DI "q")]) - -;; Wider modes with the same number of elements. -(define_mode_attr V_widen [(V8QI "V8HI") (V4HI "V4SI") (V2SI "V2DI")]) - -;; Narrower modes with the same number of elements. -(define_mode_attr V_narrow [(V8HI "V8QI") (V4SI "V4HI") (V2DI "V2SI")]) - -;; Modes with half the number of equal-sized elements. -(define_mode_attr V_HALF [(V16QI "V8QI") (V8HI "V4HI") - (V4SI "V2SI") (V4SF "V2SF") - (V2DI "DI")]) - -;; Same, but lower-case. -(define_mode_attr V_half [(V16QI "v8qi") (V8HI "v4hi") - (V4SI "v2si") (V4SF "v2sf") - (V2DI "di")]) - -;; Modes with twice the number of equal-sized elements. -(define_mode_attr V_DOUBLE [(V8QI "V16QI") (V4HI "V8HI") - (V2SI "V4SI") (V2SF "V4SF") - (DI "V2DI")]) - -;; Same, but lower-case. -(define_mode_attr V_double [(V8QI "v16qi") (V4HI "v8hi") - (V2SI "v4si") (V2SF "v4sf") - (DI "v2di")]) - -;; Modes with double-width elements. -(define_mode_attr V_double_width [(V8QI "V4HI") (V16QI "V8HI") - (V4HI "V2SI") (V8HI "V4SI") - (V2SI "DI") (V4SI "V2DI")]) - -;; Double-sized modes with the same element size. -;; Used for neon_vdup_lane, where the second operand is double-sized -;; even when the first one is quad. -(define_mode_attr V_double_vector_mode [(V16QI "V8QI") (V8HI "V4HI") - (V4SI "V2SI") (V4SF "V2SF") - (V8QI "V8QI") (V4HI "V4HI") - (V2SI "V2SI") (V2SF "V2SF")]) - -;; Mode of result of comparison operations (and bit-select operand 1). -(define_mode_attr V_cmp_result [(V8QI "V8QI") (V16QI "V16QI") - (V4HI "V4HI") (V8HI "V8HI") - (V2SI "V2SI") (V4SI "V4SI") - (V2SF "V2SI") (V4SF "V4SI") - (DI "DI") (V2DI "V2DI")]) - -;; Get element type from double-width mode, for operations where we don't care -;; about signedness. -(define_mode_attr V_if_elem [(V8QI "i8") (V16QI "i8") - (V4HI "i16") (V8HI "i16") - (V2SI "i32") (V4SI "i32") - (DI "i64") (V2DI "i64") - (V2SF "f32") (V4SF "f32")]) - -;; Same, but for operations which work on signed values. -(define_mode_attr V_s_elem [(V8QI "s8") (V16QI "s8") - (V4HI "s16") (V8HI "s16") - (V2SI "s32") (V4SI "s32") - (DI "s64") (V2DI "s64") - (V2SF "f32") (V4SF "f32")]) - -;; Same, but for operations which work on unsigned values. -(define_mode_attr V_u_elem [(V8QI "u8") (V16QI "u8") - (V4HI "u16") (V8HI "u16") - (V2SI "u32") (V4SI "u32") - (DI "u64") (V2DI "u64") - (V2SF "f32") (V4SF "f32")]) - -;; Element types for extraction of unsigned scalars. -(define_mode_attr V_uf_sclr [(V8QI "u8") (V16QI "u8") - (V4HI "u16") (V8HI "u16") - (V2SI "32") (V4SI "32") - (V2SF "32") (V4SF "32")]) - -(define_mode_attr V_sz_elem [(V8QI "8") (V16QI "8") - (V4HI "16") (V8HI "16") - (V2SI "32") (V4SI "32") - (DI "64") (V2DI "64") - (V2SF "32") (V4SF "32")]) - -;; Element sizes for duplicating ARM registers to all elements of a vector. -(define_mode_attr VD_dup [(V8QI "8") (V4HI "16") (V2SI "32") (V2SF "32")]) - -;; Opaque integer types for results of pair-forming intrinsics (vtrn, etc.) -(define_mode_attr V_PAIR [(V8QI "TI") (V16QI "OI") - (V4HI "TI") (V8HI "OI") - (V2SI "TI") (V4SI "OI") - (V2SF "TI") (V4SF "OI") - (DI "TI") (V2DI "OI")]) - -;; Same, but lower-case. -(define_mode_attr V_pair [(V8QI "ti") (V16QI "oi") - (V4HI "ti") (V8HI "oi") - (V2SI "ti") (V4SI "oi") - (V2SF "ti") (V4SF "oi") - (DI "ti") (V2DI "oi")]) - -;; Operations on two halves of a quadword vector. -(define_code_iterator vqh_ops [plus smin smax umin umax]) - -;; Same, without unsigned variants (for use with *SFmode pattern). -(define_code_iterator vqhs_ops [plus smin smax]) - -;; Assembler mnemonics for above codes. -(define_code_attr VQH_mnem [(plus "vadd") (smin "vmin") (smax "vmax") - (umin "vmin") (umax "vmax")]) - -;; Signs of above, where relevant. -(define_code_attr VQH_sign [(plus "i") (smin "s") (smax "s") (umin "u") - (umax "u")]) - -;; Extra suffix on some 64-bit insn names (to avoid collision with standard -;; names which we don't want to define). -(define_mode_attr V_suf64 [(V8QI "") (V16QI "") - (V4HI "") (V8HI "") - (V2SI "") (V4SI "") - (V2SF "") (V4SF "") - (DI "_neon") (V2DI "")]) - -;; Scalars to be presented to scalar multiplication instructions -;; must satisfy the following constraints. -;; 1. If the mode specifies 16-bit elements, the scalar must be in D0-D7. -;; 2. If the mode specifies 32-bit elements, the scalar must be in D0-D15. -;; This mode attribute is used to obtain the correct register constraints. -(define_mode_attr scalar_mul_constraint [(V4HI "x") (V2SI "t") (V2SF "t") - (V8HI "x") (V4SI "t") (V4SF "t")]) ;; Attribute used to permit string comparisons against in ;; neon_type attribute definitions. (define_attr "vqh_mnem" "vadd,vmin,vmax" (const_string "vadd")) -;; Predicates used for setting neon_type - -(define_mode_attr Is_float_mode [(V8QI "false") (V16QI "false") - (V4HI "false") (V8HI "false") - (V2SI "false") (V4SI "false") - (V2SF "true") (V4SF "true") - (DI "false") (V2DI "false")]) - -(define_mode_attr Scalar_mul_8_16 [(V8QI "true") (V16QI "true") - (V4HI "true") (V8HI "true") - (V2SI "false") (V4SI "false") - (V2SF "false") (V4SF "false") - (DI "false") (V2DI "false")]) - - -(define_mode_attr Is_d_reg [(V8QI "true") (V16QI "false") - (V4HI "true") (V8HI "false") - (V2SI "true") (V4SI "false") - (V2SF "true") (V4SF "false") - (DI "true") (V2DI "false")]) - -(define_mode_attr V_mode_nunits [(V8QI "8") (V16QI "16") - (V4HI "4") (V8HI "8") - (V2SI "2") (V4SI "4") - (V2SF "2") (V4SF "4") - (DI "1") (V2DI "2")]) - (define_insn "*neon_mov" [(set (match_operand:VD 0 "nonimmediate_operand" "=w,Uv,w, w, ?r,?w,?r,?r, ?Us") diff -rupNB -x '.svn*' baseline/trunk/source/gcc/config/arm/vec-common.md dev/trunk/source/gcc/config/arm/vec-common.md --- baseline/trunk/source/gcc/config/arm/vec-common.md 2010-08-05 17:43:36.471459000 +0100 +++ dev/trunk/source/gcc/config/arm/vec-common.md 2010-08-06 10:11:43.242365000 +0100 @@ -20,18 +20,6 @@ ;; Vector Moves -;; All integer and float modes supported by Neon and IWMMXT. -(define_mode_iterator VALL [V2DI V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) - -;; All integer and float modes supported by Neon and IWMMXT, except V2DI. -(define_mode_iterator VALLW [V2SI V4HI V8QI V2SF V4SI V8HI V16QI V4SF]) - -;; All integer modes supported by Neon and IWMMXT -(define_mode_iterator VINT [V2DI V2SI V4HI V8QI V4SI V8HI V16QI]) - -;; All integer modes supported by Neon and IWMMXT, except V2DI -(define_mode_iterator VINTW [V2SI V4HI V8QI V4SI V8HI V16QI]) - (define_expand "mov" [(set (match_operand:VALL 0 "nonimmediate_operand" "") (match_operand:VALL 1 "general_operand" ""))]