@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0
*/
@@ -64,10 +64,4 @@ struct apb_misc_gp_ctlr {
u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
};
-/* SDMMC1/3 settings from section 27.5 of T114 TRM */
-#define SDIOCFG_DRVUP_SLWF 0
-#define SDIOCFG_DRVDN_SLWR 0
-#define SDIOCFG_DRVUP 0x24
-#define SDIOCFG_DRVDN 0x14
-
#endif /* _TEGRA114_GP_PADCTRL_H_ */
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -313,6 +313,12 @@ enum pmux_func {
PMUX_FUNC_COUNT,
};
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF 0
+#define SDIOCFG_DRVDN_SLWR 0
+#define SDIOCFG_DRVUP 0x24
+#define SDIOCFG_DRVDN 0x14
+
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
#define TEGRA_PMX_SOC_HAS_DRVGRPS
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2013
+ * (C) Copyright 2010-2016
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -65,10 +65,4 @@ struct apb_misc_gp_ctlr {
u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
};
-/* SDMMC1/3 settings from section 27.5 of T114 TRM */
-#define SDIOCFG_DRVUP_SLWF 0
-#define SDIOCFG_DRVDN_SLWR 0
-#define SDIOCFG_DRVUP 0x24
-#define SDIOCFG_DRVDN 0x14
-
#endif /* _TEGRA124_GP_PADCTRL_H_ */
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2013-2016, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -342,6 +342,12 @@ enum pmux_func {
PMUX_FUNC_COUNT,
};
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF 0
+#define SDIOCFG_DRVDN_SLWR 0
+#define SDIOCFG_DRVUP 0x24
+#define SDIOCFG_DRVDN 0x14
+
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#define TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG 0x820
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
@@ -1,5 +1,5 @@
/*
- * (C) Copyright 2010-2015
+ * (C) Copyright 2010-2016
* NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
@@ -65,10 +65,4 @@ struct apb_misc_gp_ctlr {
u32 aocfg0; /* 0x1AC: APB_MISC_GP_AOCFG0PADCTRL */
};
-/* SDMMC1/3 settings from section 27.5 of T114 TRM */
-#define SDIOCFG_DRVUP_SLWF 0
-#define SDIOCFG_DRVDN_SLWR 0
-#define SDIOCFG_DRVUP 0x24
-#define SDIOCFG_DRVDN 0x14
-
#endif /* _TEGRA210_GP_PADCTRL_H_ */
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2015-2016, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -404,6 +404,12 @@ enum pmux_func {
PMUX_FUNC_COUNT,
};
+/* SDMMC1/3 settings from section 27.5 of T114 TRM */
+#define SDIOCFG_DRVUP_SLWF 0
+#define SDIOCFG_DRVDN_SLWR 0
+#define SDIOCFG_DRVUP 0x24
+#define SDIOCFG_DRVDN 0x14
+
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x8d4
#define TEGRA_PMX_SOC_HAS_IO_CLAMPING
#define TEGRA_PMX_SOC_HAS_DRVGRPS
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2012, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0
*/
@@ -46,10 +46,4 @@ struct apb_misc_gp_ctlr {
u32 sdio1cfg; /* 0xEC: APB_MISC_GP_SDIO1CFGPADCTRL */
};
-/* SDMMC1/3 settings from section 24.6 of T30 TRM */
-#define SDIOCFG_DRVUP_SLWF 1
-#define SDIOCFG_DRVDN_SLWR 1
-#define SDIOCFG_DRVUP 0x2E
-#define SDIOCFG_DRVDN 0x2A
-
#endif /* _TEGRA30_GP_PADCTRL_H_ */
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0+
*/
@@ -391,6 +391,12 @@ enum pmux_func {
PMUX_FUNC_COUNT,
};
+/* SDMMC1/3 settings from section 24.6 of T30 TRM */
+#define SDIOCFG_DRVUP_SLWF 1
+#define SDIOCFG_DRVDN_SLWR 1
+#define SDIOCFG_DRVUP 0x2E
+#define SDIOCFG_DRVDN 0x2A
+
#define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
#define TEGRA_PMX_SOC_HAS_DRVGRPS
#define TEGRA_PMX_GRPS_HAVE_LPMD
@@ -12,7 +12,6 @@
#include <dt-bindings/gpio/tegra-gpio.h>
#include <asm/gpio.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/gp_padctrl.h>
#include "pinmux-config-tamonten-ng.h"
#define PMU_I2C_ADDRESS 0x2D
@@ -11,7 +11,6 @@
#include <dt-bindings/gpio/tegra-gpio.h>
#include <asm/gpio.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/gp_padctrl.h>
#include "pinmux-config-cardhu.h"
#define PMU_I2C_ADDRESS 0x2D
@@ -1,5 +1,5 @@
/*
- * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
+ * Copyright (c) 2010-2016, NVIDIA CORPORATION. All rights reserved.
*
* SPDX-License-Identifier: GPL-2.0
*/
@@ -7,7 +7,6 @@
#include <common.h>
#include <dm.h>
#include <asm/arch/pinmux.h>
-#include <asm/arch/gp_padctrl.h>
#include "pinmux-config-dalmore.h"
#include <i2c.h>
@@ -7,7 +7,6 @@
*/
#include <common.h>
-#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pinmux.h>
#include <asm/arch-tegra/tegra.h>
#include <asm/gpio.h>