@@ -18,9 +18,6 @@
#include <asm/arch/pmu.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
-#ifdef CONFIG_TEGRA_CLOCK_SCALING
-#include <asm/arch/emc.h>
-#endif
#include "../../../drivers/usb/host/ehci-tegra-priv.h"
#ifdef CONFIG_USB_EHCI_TEGRA
#include <usb.h>
@@ -8,7 +8,6 @@
#include <common.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/emc.h>
#include <asm/arch/pmu.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
@@ -8,6 +8,20 @@
#ifndef _TEGRA_EMC_H
#define _TEGRA_EMC_H
+/* Implemented in SoC-agnostic EMC code, called by core board code */
int board_emc_init(void);
+/**
+ * Set up the EMC for the given rate. The timing parameters are retrieved
+ * from the device tree "nvidia,tegra20-emc" node and its
+ * "nvidia,tegra20-emc-table" sub-nodes.
+ *
+ * @param blob Device tree blob
+ * @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
+ * @return 0 if ok, else -ve error code (look in emc.c to decode it)
+ *
+ * Implemented by SoC-specific code.
+ */
+int tegra_set_emc(const void *blob, unsigned rate);
+
#endif
@@ -9,9 +9,10 @@
#include <fdtdec.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
-#include <asm/arch/emc.h>
#include <asm/arch/tegra.h>
#include "../apb_misc.h"
+#include "../emc.h"
+#include "emc_priv.h"
/*
* The EMC registers have shadow registers. When the EMC clock is updated
similarity index 83%
rename from arch/arm/include/asm/arch-tegra20/emc.h
rename to arch/arm/mach-tegra/tegra20/emc_priv.h
@@ -1,12 +1,12 @@
/*
* Copyright (c) 2011 The Chromium OS Authors.
- * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
+ * (C) Copyright 2010-2016 NVIDIA Corporation <www.nvidia.com>
*
* SPDX-License-Identifier: GPL-2.0+
*/
-#ifndef _ARCH_EMC_H_
-#define _ARCH_EMC_H_
+#ifndef _TEGRA20_EMC_PRIV_H
+#define _TEGRA20_EMC_PRIV_H
#include <asm/types.h>
@@ -76,17 +76,6 @@ struct emc_ctlr {
};
/**
- * Set up the EMC for the given rate. The timing parameters are retrieved
- * from the device tree "nvidia,tegra20-emc" node and its
- * "nvidia,tegra20-emc-table" sub-nodes.
- *
- * @param blob Device tree blob
- * @param rate Clock speed of memory controller in Hz (=2x memory bus rate)
- * @return 0 if ok, else -ve error code (look in emc.c to decode it)
- */
-int tegra_set_emc(const void *blob, unsigned rate);
-
-/**
* Get a pointer to the EMC controller from the device tree.
*
* @param blob Device tree blob
@@ -9,16 +9,17 @@
#include <asm/io.h>
#include <asm/errno.h>
#include <asm/arch/clock.h>
-#include <asm/arch/emc.h>
#include <asm/arch/gp_padctrl.h>
#include <asm/arch/pinmux.h>
#include <asm/arch/sdram_param.h>
#include <asm/arch/tegra.h>
#include <asm/arch-tegra/clk_rst.h>
#include "../apb_misc.h"
+#include "../emc.h"
#include "../fuse.h"
#include "../pmc.h"
#include "crypto.h"
+#include "emc_priv.h"
#include "warmboot.h"
DECLARE_GLOBAL_DATA_PTR;