| Message ID | 1460730231-1184-12-git-send-email-alex.bennee@linaro.org |
|---|---|
| State | New |
| Headers | show |
On 15/04/16 17:23, Alex Bennée wrote: > From: KONRAD Frederic <fred.konrad@greensocs.com> > > Instead of flushing each individual vCPU use the tlb_flush_page_all > functions which is async enabled for MTTCG. > > Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> > Signed-off-by: Alex Bennée <alex.bennee@linaro.org> > --- > include/exec/exec-all.h | 3 +++ > target-arm/helper.c | 12 ++---------- > 2 files changed, 5 insertions(+), 10 deletions(-) > > diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h > index 858055b..bc97683 100644 > --- a/include/exec/exec-all.h > +++ b/include/exec/exec-all.h > @@ -208,6 +208,9 @@ static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, > static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...) > { > } > +static inline void tlb_flush_page_all(target_ulong addr) > +{ > +} This change belongs to the patch which introduced the function. Kind regards, Sergey > #endif > > #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ > diff --git a/target-arm/helper.c b/target-arm/helper.c > index 19d5d52..bc9fbda 100644 > --- a/target-arm/helper.c > +++ b/target-arm/helper.c > @@ -554,21 +554,13 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, > static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - CPUState *other_cs; > - > - CPU_FOREACH(other_cs) { > - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); > - } > + tlb_flush_page_all(value & TARGET_PAGE_MASK); > } > > static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - CPUState *other_cs; > - > - CPU_FOREACH(other_cs) { > - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); > - } > + tlb_flush_page_all(value & TARGET_PAGE_MASK); > } > > static const ARMCPRegInfo cp_reginfo[] = {
Sergey Fedorov <serge.fdrv@gmail.com> writes: > On 15/04/16 17:23, Alex Bennée wrote: >> From: KONRAD Frederic <fred.konrad@greensocs.com> >> >> Instead of flushing each individual vCPU use the tlb_flush_page_all >> functions which is async enabled for MTTCG. >> >> Signed-off-by: KONRAD Frederic <fred.konrad@greensocs.com> >> Signed-off-by: Alex Bennée <alex.bennee@linaro.org> >> --- >> include/exec/exec-all.h | 3 +++ >> target-arm/helper.c | 12 ++---------- >> 2 files changed, 5 insertions(+), 10 deletions(-) >> >> diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h >> index 858055b..bc97683 100644 >> --- a/include/exec/exec-all.h >> +++ b/include/exec/exec-all.h >> @@ -208,6 +208,9 @@ static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, >> static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...) >> { >> } >> +static inline void tlb_flush_page_all(target_ulong addr) >> +{ >> +} > > This change belongs to the patch which introduced the function. Thanks, will fix. > > Kind regards, > Sergey > >> #endif >> >> #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ >> diff --git a/target-arm/helper.c b/target-arm/helper.c >> index 19d5d52..bc9fbda 100644 >> --- a/target-arm/helper.c >> +++ b/target-arm/helper.c >> @@ -554,21 +554,13 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, >> static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, >> uint64_t value) >> { >> - CPUState *other_cs; >> - >> - CPU_FOREACH(other_cs) { >> - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); >> - } >> + tlb_flush_page_all(value & TARGET_PAGE_MASK); >> } >> >> static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, >> uint64_t value) >> { >> - CPUState *other_cs; >> - >> - CPU_FOREACH(other_cs) { >> - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); >> - } >> + tlb_flush_page_all(value & TARGET_PAGE_MASK); >> } >> >> static const ARMCPRegInfo cp_reginfo[] = { -- Alex Bennée
diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 858055b..bc97683 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -208,6 +208,9 @@ static inline void tlb_flush_page_by_mmuidx(CPUState *cpu, static inline void tlb_flush_by_mmuidx(CPUState *cpu, ...) { } +static inline void tlb_flush_page_all(target_ulong addr) +{ +} #endif #define CODE_GEN_ALIGN 16 /* must be >= of the size of a icache line */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 19d5d52..bc9fbda 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -554,21 +554,13 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri, static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); - } + tlb_flush_page_all(value & TARGET_PAGE_MASK); } static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - CPUState *other_cs; - - CPU_FOREACH(other_cs) { - tlb_flush_page(other_cs, value & TARGET_PAGE_MASK); - } + tlb_flush_page_all(value & TARGET_PAGE_MASK); } static const ARMCPRegInfo cp_reginfo[] = {