diff mbox

[U-Boot,v2,04/12] ARM: omap5: add platform specific ethernet phy modes configurations

Message ID 1460450816-9943-5-git-send-email-mugunthanvnm@ti.com
State Superseded
Delegated to: Joe Hershberger
Headers show

Commit Message

Mugunthan V N April 12, 2016, 8:46 a.m. UTC 
Add platforms specific phy mode configuration bits to be used
to configure phy mode in control module.

Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
---
 arch/arm/include/asm/arch-omap5/cpu.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

Comments

Joe Hershberger April 25, 2016, 10 p.m. UTC | #1 
On Tue, Apr 12, 2016 at 3:46 AM, Mugunthan V N <mugunthanvnm@ti.com> wrote:
> Add platforms specific phy mode configuration bits to be used
> to configure phy mode in control module.
>
> Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
> Reviewed-by: Tom Rini <trini@konsulko.com>

Acked-by: Joe Hershberger <joe.hershberger@ni.com>
diff mbox

Patch

diff --git a/arch/arm/include/asm/arch-omap5/cpu.h b/arch/arm/include/asm/arch-omap5/cpu.h
index b1513e9..683d905 100644
--- a/arch/arm/include/asm/arch-omap5/cpu.h
+++ b/arch/arm/include/asm/arch-omap5/cpu.h
@@ -116,4 +116,16 @@  struct watchdog {
 #define CPSW_BASE			0x48484000
 #define CPSW_MDIO_BASE			0x48485000
 
+/* gmii_sel register defines */
+#define GMII1_SEL_MII		0x0
+#define GMII1_SEL_RMII		0x1
+#define GMII1_SEL_RGMII		0x2
+#define GMII2_SEL_MII		(GMII1_SEL_MII << 4)
+#define GMII2_SEL_RMII		(GMII1_SEL_RMII << 4)
+#define GMII2_SEL_RGMII		(GMII1_SEL_RGMII << 4)
+
+#define MII_MODE_ENABLE		(GMII1_SEL_MII | GMII2_SEL_MII)
+#define RMII_MODE_ENABLE        (GMII1_SEL_RMII | GMII2_SEL_RMII)
+#define RGMII_MODE_ENABLE	(GMII1_SEL_RGMII | GMII2_SEL_RGMII)
+
 #endif /* _CPU_H */